bus_read_1
bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
bios_sem = bus_read_1(res, eecp +
offs = bus_read_1(res, XHCI_CAPLENGTH);
(bus_read_1(amdsmb->res, register))
*byte = bus_read_1(sc->io_res, ICH_D0);
*byte = bus_read_1(sc->io_res, ICH_D0);
*word = (bus_read_1(sc->io_res,
| (bus_read_1(sc->io_res,
*rdata = (bus_read_1(sc->io_res,
| (bus_read_1(sc->io_res,
status = bus_read_1(sc->io_res, ICH_HST_STA);
sc->block_count = bus_read_1(
bus_read_1(sc->io_res,
bus_read_1(sc->io_res, ICH_HST_STA));
bus_read_1(sc->io_res, ICH_HST_STA));
#define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
#define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
#define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
cmd_result = bus_read_1(sc->sc_iomem, ASMC_MMIO_CMD);
cmd_result = bus_read_1(sc->sc_iomem, ASMC_MMIO_CMD);
type[i] = bus_read_1(sc->sc_iomem, ASMC_MMIO_DATA + i);
*len = bus_read_1(sc->sc_iomem, ASMC_MMIO_DATA + 5);
cmd_result = bus_read_1(sc->sc_iomem, ASMC_MMIO_CMD);
key[i] = bus_read_1(sc->sc_iomem, ASMC_MMIO_DATA + i);
status = bus_read_1(sc->sc_iomem, ASMC_MMIO_STATUS);
status = bus_read_1(sc->sc_iomem, ASMC_MMIO_STATUS);
if (bus_read_1(sc->sc_iomem, ASMC_MMIO_STATUS))
cmd_result = bus_read_1(sc->sc_iomem, ASMC_MMIO_CMD);
rlen = bus_read_1(sc->sc_iomem, ASMC_MMIO_DATA_LEN);
buf[i] = bus_read_1(sc->sc_iomem, ASMC_MMIO_DATA + i);
return (bus_read_1(sc->mem_res, off));
bus_read_1((bt)->port, reg)
return bus_read_1(sc->mem_res, off);
return bus_read_1(sc->mem_res[slot->num], off);
#define INB_OFF(o) bus_read_1(np->io_res, (o))
#define INB_OFF(o) bus_read_1(np->mmio_res, (o))
return (bus_read_1(res, 1)); /* Data */
val = bus_read_1(pmres, AMDFCH41_PM_DECODE_EN0);
val = bus_read_1(pmres, AMDFCH41_PM_DECODE_EN0);
val = bus_read_1(pmres, AMDFCH41_PM_ISA_CTRL);
val = bus_read_1(pmres, AMDFCH41_PM_DECODE_EN3);
val = bus_read_1(pmres, AMDFCH41_PM_DECODE_EN3);
bus_read_1((sc)->tco_res, (off))
bus_read_1((sc)->ipmi_io_res[0], (sc)->ipmi_io_spacing * (x))
bus_read_1((sc)->ipmi_io_res[(x)], 0)
(bus_read_1(amdpm->res, register))
return (bus_read_1(res, 1)); /* Data */
if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
(bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
*byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
*byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
*byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
*word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
*word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
#define vtmmio_read_config_1(sc, o) bus_read_1((sc)->res[0], (o))
#define vtpci_read_config_1(sc, o) bus_read_1((sc)->vtpci_res, (o))