ata_mode2idx
int ata_mode2idx(int mode);
piotimings[ata_mode2idx(mode)], 4);
pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
(piotimings[ata_mode2idx(piomode)] << offset), 4);
timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
new40 = timings[ata_mode2idx(mode)] << 8;
new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
(timings[ata_mode2idx(mode)] & 0x03);
chtiming[ata_mode2idx(mode)])
chtiming[ata_mode2idx(mode)], 1);
new40 = timings[ata_mode2idx(mode)] << 8;
new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
(timings[ata_mode2idx(mode)] & 0x03);
piotiming[ata_mode2idx(mode)], 4);
pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
(piotimings[ata_mode2idx(mode)] << offset), 4);
pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
pci_write_config(gparent, reg - 0x08,timings[ata_mode2idx(mode)],1);