Symbol: amdgpu_crtc
sys/dev/drm/amd/amdgpu/amdgpu_device.c
2829
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_device.c
2833
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/amdgpu_device.c
2834
struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/amdgpu_device.c
2943
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_device.c
2945
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/amdgpu_device.c
2946
struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/amdgpu_device.c
2952
amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
100
amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) {
sys/dev/drm/amd/amdgpu/amdgpu_display.c
112
amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
117
amdgpu_crtc->crtc_id, amdgpu_crtc, work);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
154
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
171
work->crtc_id = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
220
if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
sys/dev/drm/amd/amdgpu/amdgpu_display.c
227
amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
228
amdgpu_crtc->pflip_works = work;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
232
amdgpu_crtc->crtc_id, amdgpu_crtc, work);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
667
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
674
amdgpu_crtc->h_border = 0;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
675
amdgpu_crtc->v_border = 0;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
686
amdgpu_crtc->rmx_type = RMX_OFF;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
689
amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
691
amdgpu_crtc->rmx_type = RMX_OFF;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
693
memcpy(&amdgpu_crtc->native_mode,
sys/dev/drm/amd/amdgpu/amdgpu_display.c
697
dst_v = amdgpu_crtc->native_mode.vdisplay;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
699
dst_h = amdgpu_crtc->native_mode.hdisplay;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
708
amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
710
amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
712
amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
714
amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
715
amdgpu_crtc->rmx_type = RMX_FULL;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
717
dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
719
dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
722
if (amdgpu_crtc->rmx_type != RMX_OFF) {
sys/dev/drm/amd/amdgpu/amdgpu_display.c
726
amdgpu_crtc->vsc.full = dfixed_div(a, b);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
729
amdgpu_crtc->hsc.full = dfixed_div(a, b);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
731
amdgpu_crtc->vsc.full = dfixed_const(1);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
732
amdgpu_crtc->hsc.full = dfixed_const(1);
sys/dev/drm/amd/amdgpu/amdgpu_display.c
76
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
sys/dev/drm/amd/amdgpu/amdgpu_display.c
78
struct drm_crtc *crtc = &amdgpu_crtc->base;
sys/dev/drm/amd/amdgpu/amdgpu_display.c
93
if (amdgpu_crtc->enabled &&
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
123
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
130
amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
131
if (amdgpu_crtc->enabled) {
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
132
adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
144
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
150
amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
151
if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
153
amdgpu_crtc->hw_mode.crtc_htotal *
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
154
(amdgpu_crtc->hw_mode.crtc_vblank_end -
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
155
amdgpu_crtc->hw_mode.crtc_vdisplay +
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
156
(amdgpu_crtc->v_border * 2));
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
158
vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
171
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
176
amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
177
if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
178
vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
sys/dev/drm/amd/amdgpu/amdgpu_kms.c
494
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_kms.c
495
ui32 = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/amdgpu_mode.h
327
struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
sys/dev/drm/amd/amdgpu/amdgpu_mode.h
56
#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
264
struct amdgpu_crtc *test_amdgpu_crtc;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
291
struct amdgpu_crtc *test_amdgpu_crtc;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
318
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
321
struct amdgpu_crtc *test_amdgpu_crtc;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
324
adjusted_clock = amdgpu_crtc->adjusted_clock;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
336
if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
345
(amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&
sys/dev/drm/amd/amdgpu/atombios_crtc.c
115
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
124
args.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
132
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
140
args.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
148
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
156
args.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
164
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
172
args.ucDispPipeId = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
193
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
201
args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));
sys/dev/drm/amd/amdgpu/atombios_crtc.c
203
cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2));
sys/dev/drm/amd/amdgpu/atombios_crtc.c
204
args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2));
sys/dev/drm/amd/amdgpu/atombios_crtc.c
206
cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2));
sys/dev/drm/amd/amdgpu/atombios_crtc.c
208
cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
212
cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
215
args.ucH_Border = amdgpu_crtc->h_border;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
216
args.ucV_Border = amdgpu_crtc->v_border;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
230
args.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
308
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
311
struct drm_encoder *encoder = amdgpu_crtc->encoder;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
318
int bpc = amdgpu_crtc->bpc;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
324
amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
339
if (amdgpu_crtc->ss_enabled) {
sys/dev/drm/amd/amdgpu/atombios_crtc.c
340
if (amdgpu_crtc->ss.refdiv) {
sys/dev/drm/amd/amdgpu/atombios_crtc.c
341
amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
342
amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
343
amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
352
amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
354
amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
394
if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
sys/dev/drm/amd/amdgpu/atombios_crtc.c
407
if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
sys/dev/drm/amd/amdgpu/atombios_crtc.c
435
amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
436
amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
437
amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
440
amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
441
amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
442
amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
45
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
52
args.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
54
switch (amdgpu_crtc->rmx_type) {
sys/dev/drm/amd/amdgpu/atombios_crtc.c
75
args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
750
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
754
to_amdgpu_encoder(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
755
int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
757
amdgpu_crtc->bpc = 8;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
758
amdgpu_crtc->ss_enabled = false;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
76
args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
761
(amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
sys/dev/drm/amd/amdgpu/atombios_crtc.c
764
amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
77
args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
773
amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
78
args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
780
amdgpu_crtc->ss_enabled =
sys/dev/drm/amd/amdgpu/atombios_crtc.c
781
amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
786
amdgpu_crtc->ss_enabled =
sys/dev/drm/amd/amdgpu/atombios_crtc.c
788
&amdgpu_crtc->ss,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
793
amdgpu_crtc->ss_enabled =
sys/dev/drm/amd/amdgpu/atombios_crtc.c
795
&amdgpu_crtc->ss,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
800
amdgpu_crtc->ss_enabled =
sys/dev/drm/amd/amdgpu/atombios_crtc.c
802
&amdgpu_crtc->ss,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
812
amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
819
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
823
to_amdgpu_encoder(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
828
int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
832
(amdgpu_crtc->bpc > 8))
sys/dev/drm/amd/amdgpu/atombios_crtc.c
833
clock = amdgpu_crtc->adjusted_clock;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
835
switch (amdgpu_crtc->pll_id) {
sys/dev/drm/amd/amdgpu/atombios_crtc.c
850
pll->flags = amdgpu_crtc->pll_flags;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
851
pll->reference_div = amdgpu_crtc->pll_reference_div;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
852
pll->post_div = amdgpu_crtc->pll_post_div;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
854
amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
857
amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
858
amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
860
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
863
amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
865
if (amdgpu_crtc->ss_enabled) {
sys/dev/drm/amd/amdgpu/atombios_crtc.c
869
(u32)amdgpu_crtc->ss.percentage) /
sys/dev/drm/amd/amdgpu/atombios_crtc.c
870
(100 * (u32)amdgpu_crtc->ss.percentage_divider);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
871
amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
872
amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
sys/dev/drm/amd/amdgpu/atombios_crtc.c
874
if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
sys/dev/drm/amd/amdgpu/atombios_crtc.c
875
step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
sys/dev/drm/amd/amdgpu/atombios_crtc.c
878
step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
sys/dev/drm/amd/amdgpu/atombios_crtc.c
88
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
880
amdgpu_crtc->ss.step = step_size;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
882
amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
883
amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
94
args.ucScaler = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_crtc.c
96
switch (amdgpu_crtc->rmx_type) {
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1541
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1557
args.v1.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1596
args.v2.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1664
args.v3.ucCRTC = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/atombios_encoders.c
423
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
424
bpc = amdgpu_crtc->bpc;
sys/dev/drm/amd/amdgpu/atombios_encoders.c
873
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
874
pll_id = amdgpu_crtc->pll_id;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1014
struct amdgpu_crtc *amdgpu_crtc,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1017
struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1024
if (amdgpu_crtc->base.enabled && num_heads && mode) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1049
wm_high.vsc = amdgpu_crtc->vsc;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1051
if (amdgpu_crtc->rmx_type != RMX_OFF)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1088
wm_low.vsc = amdgpu_crtc->vsc;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1090
if (amdgpu_crtc->rmx_type != RMX_OFF)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1112
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1114
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1115
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1118
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1121
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1122
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1125
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1127
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1130
amdgpu_crtc->line_time = line_time;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1131
amdgpu_crtc->wm_high = latency_watermark_a;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1132
amdgpu_crtc->wm_low = latency_watermark_b;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1134
amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1519
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1534
amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1566
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1567
bpc = amdgpu_crtc->bpc;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1798
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1803
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1805
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1807
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1812
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1817
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1819
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1826
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1996
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1999
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2001
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2003
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2005
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2007
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2009
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2010
WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2017
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2022
WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2027
WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2028
WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2029
WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2030
WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2031
WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2032
WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2035
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2039
WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2044
WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2048
WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2052
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2074
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2077
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2082
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2087
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2094
DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2096
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2099
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2101
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2103
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2105
tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2107
WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2109
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2112
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2114
WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2116
WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2117
WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2118
WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2120
WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2121
WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2122
WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2124
WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2125
WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2127
WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2132
WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2138
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2142
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2144
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2147
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2149
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2152
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2154
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2157
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2160
WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2164
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2166
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2226
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2232
if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2264
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2267
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2272
WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2277
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2281
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2283
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2288
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2292
WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2293
upper_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2294
WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2295
lower_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2297
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2300
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2306
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2310
amdgpu_crtc->cursor_x = x;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2311
amdgpu_crtc->cursor_y = y;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2319
xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2323
yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2327
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2328
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2329
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2330
((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
sys/dev/drm/amd/amdgpu/dce_v10_0.c
235
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2355
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2367
if ((width > amdgpu_crtc->max_cursor_width) ||
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2368
(height > amdgpu_crtc->max_cursor_height)) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2375
DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
239
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2393
amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2397
if (width != amdgpu_crtc->cursor_width ||
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2398
height != amdgpu_crtc->cursor_height ||
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2399
hot_x != amdgpu_crtc->cursor_hot_x ||
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2400
hot_y != amdgpu_crtc->cursor_hot_y) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2403
x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2404
y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2408
amdgpu_crtc->cursor_width = width;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2409
amdgpu_crtc->cursor_height = height;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2410
amdgpu_crtc->cursor_hot_x = hot_x;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2411
amdgpu_crtc->cursor_hot_y = hot_y;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2418
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2419
struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
242
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2425
drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2428
amdgpu_crtc->cursor_bo = obj;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2434
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2436
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2439
dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
244
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2440
amdgpu_crtc->cursor_y);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2459
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2462
kfree(amdgpu_crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
247
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2478
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2483
amdgpu_crtc->enabled = true;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2490
amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
250
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2500
if (amdgpu_crtc->enabled) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2506
amdgpu_crtc->enabled = false;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2529
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2557
i != amdgpu_crtc->crtc_id &&
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2558
amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2566
switch (amdgpu_crtc->pll_id) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2571
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2578
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2579
amdgpu_crtc->adjusted_clock = 0;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2580
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2581
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2589
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2591
if (!amdgpu_crtc->adjusted_clock)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2601
amdgpu_crtc->hw_mode = *adjusted_mode;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2610
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2617
amdgpu_crtc->encoder = encoder;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2618
amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2622
if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2623
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2624
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2632
amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2634
if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2635
!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2667
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2669
amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2671
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2674
drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2676
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2677
amdgpu_crtc->crtc_id = index;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2678
adev->mode_info.crtcs[index] = amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2680
amdgpu_crtc->max_cursor_width = 128;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2681
amdgpu_crtc->max_cursor_height = 128;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2682
adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2683
adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2685
switch (amdgpu_crtc->crtc_id) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2688
amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2691
amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2694
amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2697
amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2700
amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2703
amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2707
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2708
amdgpu_crtc->adjusted_clock = 0;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2709
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2710
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2711
drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3110
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3114
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3127
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3131
works = amdgpu_crtc->pflip_works;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3132
if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3135
amdgpu_crtc->pflip_status,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3142
amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3143
amdgpu_crtc->pflip_works = NULL;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3147
drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3151
drm_crtc_vblank_put(&amdgpu_crtc->base);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
496
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
564
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
582
struct amdgpu_crtc *amdgpu_crtc,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
586
u32 pipe_offset = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
595
if (amdgpu_crtc->base.enabled && mode) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
615
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
617
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
630
if (amdgpu_crtc->base.enabled && mode) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1040
struct amdgpu_crtc *amdgpu_crtc,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1043
struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1050
if (amdgpu_crtc->base.enabled && num_heads && mode) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1075
wm_high.vsc = amdgpu_crtc->vsc;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1077
if (amdgpu_crtc->rmx_type != RMX_OFF)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1114
wm_low.vsc = amdgpu_crtc->vsc;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1116
if (amdgpu_crtc->rmx_type != RMX_OFF)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1138
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1140
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1141
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1144
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1147
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1148
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1151
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1153
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1156
amdgpu_crtc->line_time = line_time;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1157
amdgpu_crtc->wm_high = latency_watermark_a;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1158
amdgpu_crtc->wm_low = latency_watermark_b;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1160
amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1561
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1576
amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1608
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1609
bpc = amdgpu_crtc->bpc;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1840
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1845
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1847
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1849
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1854
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1859
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1861
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1868
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2038
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2041
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2043
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2045
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2047
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2049
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2051
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2052
WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2059
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2064
WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2069
WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2070
WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2071
WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2072
WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2073
WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2074
WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2077
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2081
WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2086
WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2090
WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2094
WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2116
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2119
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2124
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2129
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2136
DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2138
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2140
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2142
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2144
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2146
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2148
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2150
WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2152
WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2153
WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2154
WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2156
WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2157
WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2158
WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2160
WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2161
WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2163
WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2168
WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2174
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2178
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2180
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2182
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2184
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2186
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2188
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2190
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2193
WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2197
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2199
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2259
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2270
to_amdgpu_encoder(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2273
if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2301
if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2343
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2346
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2351
WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2356
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2360
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2362
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2367
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2371
WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2372
upper_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2373
WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2374
lower_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2376
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2379
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2385
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2389
amdgpu_crtc->cursor_x = x;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2390
amdgpu_crtc->cursor_y = y;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2398
xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2402
yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2406
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2407
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2408
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2409
((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2434
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2446
if ((width > amdgpu_crtc->max_cursor_width) ||
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2447
(height > amdgpu_crtc->max_cursor_height)) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2454
DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2472
amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2476
if (width != amdgpu_crtc->cursor_width ||
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2477
height != amdgpu_crtc->cursor_height ||
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2478
hot_x != amdgpu_crtc->cursor_hot_x ||
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2479
hot_y != amdgpu_crtc->cursor_hot_y) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2482
x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2483
y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2487
amdgpu_crtc->cursor_width = width;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2488
amdgpu_crtc->cursor_height = height;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2489
amdgpu_crtc->cursor_hot_x = hot_x;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2490
amdgpu_crtc->cursor_hot_y = hot_y;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2497
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2498
struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2504
drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2507
amdgpu_crtc->cursor_bo = obj;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2513
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2515
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2518
dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2519
amdgpu_crtc->cursor_y);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
253
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2538
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2541
kfree(amdgpu_crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2557
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2562
amdgpu_crtc->enabled = true;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2569
amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
257
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2579
if (amdgpu_crtc->enabled) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2585
amdgpu_crtc->enabled = false;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
260
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2608
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
262
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2636
i != amdgpu_crtc->crtc_id &&
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2637
amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2645
switch (amdgpu_crtc->pll_id) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
265
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2650
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2660
amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2667
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2668
amdgpu_crtc->adjusted_clock = 0;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2669
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2670
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2678
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
268
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2682
if (!amdgpu_crtc->adjusted_clock)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2690
to_amdgpu_encoder(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2692
amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2695
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2696
amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2699
amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2709
amdgpu_crtc->hw_mode = *adjusted_mode;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2718
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2725
amdgpu_crtc->encoder = encoder;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2726
amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2730
if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2731
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2732
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2740
amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2742
if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2743
!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2775
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2777
amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2779
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2782
drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2784
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2785
amdgpu_crtc->crtc_id = index;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2786
adev->mode_info.crtcs[index] = amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2788
amdgpu_crtc->max_cursor_width = 128;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2789
amdgpu_crtc->max_cursor_height = 128;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2790
adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2791
adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2793
switch (amdgpu_crtc->crtc_id) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2796
amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2799
amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2802
amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2805
amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2808
amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2811
amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2815
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2816
amdgpu_crtc->adjusted_clock = 0;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2817
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2818
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2819
drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3236
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3240
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3253
if(amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3257
works = amdgpu_crtc->pflip_works;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3258
if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3261
amdgpu_crtc->pflip_status,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3268
amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3269
amdgpu_crtc->pflip_works = NULL;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3273
drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3277
drm_crtc_vblank_put(&amdgpu_crtc->base);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
522
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
590
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
608
struct amdgpu_crtc *amdgpu_crtc,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
612
u32 pipe_offset = amdgpu_crtc->crtc_id;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
621
if (amdgpu_crtc->base.enabled && mode) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
641
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
643
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
656
if (amdgpu_crtc->base.enabled && mode) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1023
wm_low.vsc = amdgpu_crtc->vsc;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1025
if (amdgpu_crtc->rmx_type != RMX_OFF)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1047
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1051
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1052
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1056
tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1059
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1060
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1064
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1067
amdgpu_crtc->line_time = line_time;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1068
amdgpu_crtc->wm_high = latency_watermark_a;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1069
amdgpu_crtc->wm_low = latency_watermark_b;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1071
amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1470
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1482
WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1515
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1516
bpc = amdgpu_crtc->bpc;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1727
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1732
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1734
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1736
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1741
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1746
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1748
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1755
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
183
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
sys/dev/drm/amd/amdgpu/dce_v8_0.c
186
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
sys/dev/drm/amd/amdgpu/dce_v8_0.c
189
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1911
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1913
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1915
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1917
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1919
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
192
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1921
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1922
WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1929
WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1936
WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1937
WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1938
WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1939
WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1940
WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1941
WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1944
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1948
WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
195
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1953
WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1957
WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1961
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1983
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1986
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1989
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1994
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2000
DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2002
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2005
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2007
WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2009
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2013
WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2015
WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2016
WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2017
WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2019
WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2020
WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2021
WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2023
WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2024
WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2026
WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2031
WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2037
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2041
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2044
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2047
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2051
WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2055
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2116
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2122
if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2167
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2170
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2175
WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2180
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2183
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2190
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2193
WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2194
upper_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2195
WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2196
lower_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2198
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2207
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2211
amdgpu_crtc->cursor_x = x;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2212
amdgpu_crtc->cursor_y = y;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2220
xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2224
yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2228
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2229
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2230
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2231
((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2256
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2268
if ((width > amdgpu_crtc->max_cursor_width) ||
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2269
(height > amdgpu_crtc->max_cursor_height)) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2276
DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2294
amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2298
if (width != amdgpu_crtc->cursor_width ||
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2299
height != amdgpu_crtc->cursor_height ||
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2300
hot_x != amdgpu_crtc->cursor_hot_x ||
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2301
hot_y != amdgpu_crtc->cursor_hot_y) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2304
x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2305
y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2309
amdgpu_crtc->cursor_width = width;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2310
amdgpu_crtc->cursor_height = height;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2311
amdgpu_crtc->cursor_hot_x = hot_x;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2312
amdgpu_crtc->cursor_hot_y = hot_y;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2319
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2320
struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2326
drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2329
amdgpu_crtc->cursor_bo = obj;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2335
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2337
if (amdgpu_crtc->cursor_bo) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2340
dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2341
amdgpu_crtc->cursor_y);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2360
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2363
kfree(amdgpu_crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2379
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2384
amdgpu_crtc->enabled = true;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2391
amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2401
if (amdgpu_crtc->enabled) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2407
amdgpu_crtc->enabled = false;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2430
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2458
i != amdgpu_crtc->crtc_id &&
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2459
amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2467
switch (amdgpu_crtc->pll_id) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2471
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2479
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2486
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2487
amdgpu_crtc->adjusted_clock = 0;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2488
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2489
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2497
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2499
if (!amdgpu_crtc->adjusted_clock)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2509
amdgpu_crtc->hw_mode = *adjusted_mode;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2518
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2525
amdgpu_crtc->encoder = encoder;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2526
amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2530
if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2531
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2532
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2540
amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2542
if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2543
!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2575
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2577
amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2579
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2582
drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2584
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2585
amdgpu_crtc->crtc_id = index;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2586
adev->mode_info.crtcs[index] = amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2588
amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2589
amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2590
adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2591
adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2593
amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2595
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2596
amdgpu_crtc->adjusted_clock = 0;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2597
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2598
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2599
drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3079
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3083
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3096
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3100
works = amdgpu_crtc->pflip_works;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3101
if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3104
amdgpu_crtc->pflip_status,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3111
amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3112
amdgpu_crtc->pflip_works = NULL;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3116
drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3120
drm_crtc_vblank_put(&amdgpu_crtc->base);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
436
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
501
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
519
struct amdgpu_crtc *amdgpu_crtc,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
523
u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
532
if (amdgpu_crtc->base.enabled && mode) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
552
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
565
if (amdgpu_crtc->base.enabled && mode) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
949
struct amdgpu_crtc *amdgpu_crtc,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
952
struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
959
if (amdgpu_crtc->base.enabled && num_heads && mode) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
984
wm_high.vsc = amdgpu_crtc->vsc;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
986
if (amdgpu_crtc->rmx_type != RMX_OFF)
sys/dev/drm/amd/amdgpu/dce_virtual.c
111
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_virtual.c
114
kfree(amdgpu_crtc);
sys/dev/drm/amd/amdgpu/dce_virtual.c
130
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_virtual.c
138
amdgpu_crtc->enabled = true;
sys/dev/drm/amd/amdgpu/dce_virtual.c
141
amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_virtual.c
149
amdgpu_crtc->enabled = false;
sys/dev/drm/amd/amdgpu/dce_virtual.c
167
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_virtual.c
184
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_virtual.c
185
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_virtual.c
186
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_virtual.c
194
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/amdgpu/dce_virtual.c
197
amdgpu_crtc->hw_mode = *adjusted_mode;
sys/dev/drm/amd/amdgpu/dce_virtual.c
236
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_virtual.c
238
amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
sys/dev/drm/amd/amdgpu/dce_virtual.c
240
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_virtual.c
243
drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
sys/dev/drm/amd/amdgpu/dce_virtual.c
245
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
sys/dev/drm/amd/amdgpu/dce_virtual.c
246
amdgpu_crtc->crtc_id = index;
sys/dev/drm/amd/amdgpu/dce_virtual.c
247
adev->mode_info.crtcs[index] = amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_virtual.c
249
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
sys/dev/drm/amd/amdgpu/dce_virtual.c
250
amdgpu_crtc->encoder = NULL;
sys/dev/drm/amd/amdgpu/dce_virtual.c
251
amdgpu_crtc->connector = NULL;
sys/dev/drm/amd/amdgpu/dce_virtual.c
252
amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
sys/dev/drm/amd/amdgpu/dce_virtual.c
253
drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
sys/dev/drm/amd/amdgpu/dce_virtual.c
659
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/amdgpu/dce_virtual.c
662
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
sys/dev/drm/amd/amdgpu/dce_virtual.c
670
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/dce_virtual.c
674
works = amdgpu_crtc->pflip_works;
sys/dev/drm/amd/amdgpu/dce_virtual.c
675
if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
sys/dev/drm/amd/amdgpu/dce_virtual.c
678
amdgpu_crtc->pflip_status,
sys/dev/drm/amd/amdgpu/dce_virtual.c
685
amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
sys/dev/drm/amd/amdgpu/dce_virtual.c
686
amdgpu_crtc->pflip_works = NULL;
sys/dev/drm/amd/amdgpu/dce_virtual.c
690
drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
sys/dev/drm/amd/amdgpu/dce_virtual.c
694
drm_crtc_vblank_put(&amdgpu_crtc->base);
sys/dev/drm/amd/amdgpu/dce_virtual.c
702
struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
sys/dev/drm/amd/amdgpu/dce_virtual.c
703
struct amdgpu_crtc, vblank_timer);
sys/dev/drm/amd/amdgpu/dce_virtual.c
704
struct drm_device *ddev = amdgpu_crtc->base.dev;
sys/dev/drm/amd/amdgpu/dce_virtual.c
707
drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/dce_virtual.c
708
dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
sys/dev/drm/amd/amdgpu/si_dpm.c
5778
struct amdgpu_crtc *amdgpu_crtc = NULL;
sys/dev/drm/amd/amdgpu/si_dpm.c
5786
amdgpu_crtc = adev->mode_info.crtcs[i];
sys/dev/drm/amd/amdgpu/si_dpm.c
5791
if (amdgpu_crtc == NULL)
sys/dev/drm/amd/amdgpu/si_dpm.c
5794
if (amdgpu_crtc->line_time <= 0)
sys/dev/drm/amd/amdgpu/si_dpm.c
5799
amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
sys/dev/drm/amd/amdgpu/si_dpm.c
5804
amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
sys/dev/drm/amd/amdgpu/si_dpm.c
5809
amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
167
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
190
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2004
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
240
static struct amdgpu_crtc *
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
246
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
254
amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
256
if (amdgpu_crtc->otg_inst == otg_inst)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
257
return amdgpu_crtc;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
265
struct amdgpu_crtc *amdgpu_crtc;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
270
amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
274
if (amdgpu_crtc == NULL) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
281
if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
283
amdgpu_crtc->pflip_status,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
285
amdgpu_crtc->crtc_id,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
286
amdgpu_crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
293
if (amdgpu_crtc->event) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
295
drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
297
drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
300
amdgpu_crtc->event = NULL;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3011
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
305
amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
309
__func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
311
drm_crtc_vblank_put(&amdgpu_crtc->base);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
318
struct amdgpu_crtc *acrtc;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3692
struct amdgpu_crtc *acrtc = NULL;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3704
acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4183
struct amdgpu_crtc *acrtc,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4230
struct amdgpu_crtc *acrtc,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4242
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4253
if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4254
(plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4268
xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4272
yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4290
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4301
amdgpu_crtc->crtc_id,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4317
amdgpu_crtc->cursor_width = plane->state->crtc_w;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4318
amdgpu_crtc->cursor_height = plane->state->crtc_h;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4341
static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4387
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4588
struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4718
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4765
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4841
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4864
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4911
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4982
struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5043
struct amdgpu_crtc *disconnected_acrtc;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5174
struct amdgpu_crtc *acrtc = NULL;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5718
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
539
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];