BIT_8
#define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */
#define BMU_START BIT_8 /* Start Rx/Tx Queue */
#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8
#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
#define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */
#define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */
#define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */
#define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */
#define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occured */
#define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */
#define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */
#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */
#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */
#define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */
#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
#define PCI_PATCH_DIR_0 BIT_8
#define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */
#define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */
#define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */
#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */
#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */
BIT_11 | BIT_10 | BIT_9 | BIT_8,
BIT_10 | BIT_9 | BIT_8);
Data &= ~BIT_8;
Data |= BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data |= BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data |= BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data |= BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data |= BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
Data &= ~BIT_8;
TmpUshort = (PhyRegValue & BIT_8) ? 0 : BIT_15;
TmpUshort = (PhyRegValue & BIT_8) ? BIT_1 : 0;
ClearEthPhyBit(sc, 0x14, BIT_8);
ClearEthPhyBit(sc, 0x14, BIT_8);
ClearEthPhyBit(sc, 0x14, BIT_8);
ClearEthPhyBit(sc, 0x14, BIT_8);
ClearEthPhyBit(sc, 0x14, BIT_8);
BIT_15|BIT_14|BIT_13|BIT_12|BIT_11|BIT_10|BIT_8,
BIT_11|BIT_10|BIT_9|BIT_8);
BIT_15|BIT_14|BIT_13|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
ClearEthPhyOcpBit(sc, 0xAC08, BIT_8);
SetEthPhyOcpBit(sc, 0xA438, BIT_8);
ClearEthPhyOcpBit(sc, 0xA438, BIT_8);
ClearEthPhyOcpBit(sc, 0xAC08, BIT_8);
ClearEthPhyOcpBit(sc, 0xAC80, BIT_9|BIT_8);
SetEthPhyOcpBit(sc, 0xA438, BIT_8);
SetEthPhyOcpBit(sc, 0xBCCA, (BIT_9 | BIT_8));
BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8,
SetEthPhyBit(sc, 0x10, BIT_8 | BIT_9);
ClearEthPhyBit(sc, 0x10, BIT_8);
ClearEthPhyBit(sc, 0x10, BIT_8 | BIT_9);
if ((CSR_READ_2(sc, RE_IntrMitigate) & (BIT_0 | BIT_1 | BIT_8)) == (BIT_0 | BIT_1 | BIT_8))
ioffset_p1 = ((TmpUshort & (BIT_8|BIT_7|BIT_6|BIT_5))>>5);
return (MP_ReadMcuAccessRegWord(sc, 0xD42C) & BIT_8);
MP_WriteMcuAccessRegWord(sc, 0xD408, MP_ReadMcuAccessRegWord(sc, 0xD408) & ~(BIT_8));
BIT_8,
Data32 |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
SetPCIePhyBit(sc, 0x19, BIT_8);
SetPCIePhyBit(sc, 0x19, BIT_8);
Data32 |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
Data32 |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
Data32 |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
(BIT_13|BIT_12|BIT_10|BIT_9|BIT_8|BIT_7|BIT_6|BIT_4),
(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
ClearPCIePhyBit(sc, 0x0D, BIT_8);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
Data32 |= BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12;
ClearPCIePhyBit(sc, 0x0C, (BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4));
BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5,
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
Data32 |= BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12;
(BIT_12| BIT_8)
(BIT_12| BIT_8)
data16 &= ~( BIT_10 | BIT_9 | BIT_8);
data16 &= ~(BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5);
data16 &= ~(BIT_14 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 |= (BIT_8|BIT_9|BIT_10|BIT_11|BIT_12);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data |= BIT_8;
data &= ~BIT_8;