BIT_7
#define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */
#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */
#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7
#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */
#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
#define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */
#define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */
#define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/
#define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */
#define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */
#define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */
#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
#define PCI_EXT_PATCH_3 BIT_7
#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
#define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */
#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
#define Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */
#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */
#define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */
ClearEthPhyOcpBit(sc, 0xA428, BIT_7);
ClearEthPhyOcpBit(sc, 0xA428, BIT_7);
ClearEthPhyBit(sc, 0x14, BIT_7);
PhyRegValue |= (BIT_7);
PhyRegValue &= ~(BIT_6|BIT_7);
PhyRegValue &= ~(BIT_7);
PhyRegValue &= ~(BIT_7);
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7);
PhyRegValue &= ~(BIT_7);
PhyRegValue &= ~(BIT_7);
PhyRegValue |= BIT_7;
PhyRegValue &= ~(BIT_7);
PhyRegValue &= ~(BIT_7);
if (PhyRegValue & BIT_7)
PhyRegValue &= ~BIT_7;
if (PhyRegValue & BIT_7)
if (MP_ReadPhyUshort(sc, 0x1c) & BIT_7)
if (PhyRegValue & BIT_7)
if (PhyRegValue & BIT_7)
if (PhyRegValue & BIT_7)
if (PhyRegValue & BIT_7)
if (PhyRegValue & BIT_7)
if (PhyRegValue & BIT_7)
if (PhyRegValue & BIT_7)
SetEthPhyOcpBit(sc, 0xB820, BIT_7);
ClearEthPhyOcpBit(sc, 0xB820, BIT_7);
SetEthPhyOcpBit(sc, 0xB820, BIT_7);
ClearEthPhyOcpBit(sc, 0xB820, BIT_7);
SetEthPhyBit(sc, 0x11, BIT_7);
SetEthPhyBit(sc, 0x11, BIT_7);
SetEthPhyBit(sc, 0x11, BIT_7);
SetEthPhyBit(sc, 0x11, BIT_7);
SetEthPhyBit(sc, 0x11, BIT_7);
BIT_7|BIT_6|BIT_5,
ClearEthPhyOcpBit(sc, 0xAC14, BIT_7);
BIT_7|BIT_6|BIT_5|BIT_4,
SetEthPhyBit(sc, 0x11, BIT_7);
CSR_WRITE_1(sc, RE_TwiCmdReg, CSR_READ_1(sc, RE_TwiCmdReg) | (BIT_7));
CSR_WRITE_1(sc, RE_TwiCmdReg, CSR_READ_1(sc, RE_TwiCmdReg) & ~(BIT_7));
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7);
CSR_WRITE_1(sc, 0xF1, CSR_READ_1(sc, 0xF1) & ~BIT_7);
ioffset_p3 = ((TmpUshort & BIT_7) >>7);
ioffset_p1 = ((TmpUshort & (BIT_8|BIT_7|BIT_6|BIT_5))>>5);
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7);
CSR_WRITE_1(sc, 0xF1, CSR_READ_1(sc, 0xF1) & ~BIT_7);
CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) | (BIT_6|BIT_7));
CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) |BIT_7);
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
data16 |= BIT_7;
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
Data8 |= (BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
data16 &= ~(BIT_7 | BIT_6);
data16 |= BIT_7;
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
data16 &= ~(BIT_7 | BIT_6);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
Data32 |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
(BIT_13|BIT_12|BIT_10|BIT_9|BIT_8|BIT_7|BIT_6|BIT_4),
(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
SetPCIePhyBit(sc, 0x00, BIT_7);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
Data32 |= BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12;
CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
ClearPCIePhyBit(sc, 0x0C, (BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4));
BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5,
data16 |= BIT_7;
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
Data32 |= BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12;
CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) & ~BIT_7);
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_7);
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_7);
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_7);
CSR_WRITE_1(sc, 0xF1, CSR_READ_1(sc, 0xF1) & ~BIT_7);
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7);
CSR_WRITE_1(sc, 0xF1, CSR_READ_1(sc, 0xF1) & ~BIT_7);
Data8 &= ~(BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_7);
ClearMcuAccessRegBit(sc, 0xE052, BIT_7);
data16 &= ~(BIT_7);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 |= BIT_7;
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_7);
CSR_WRITE_1(sc, 0xF1, CSR_READ_1(sc, 0xF1) & ~BIT_7);
CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) & ~(BIT_6|BIT_7));
ClearEthPhyBit(sc, 0x14, BIT_7);
if ((CSR_READ_1(sc, RE_CFG4)&RL_CFG4_CUSTOMIZED_LED) && (CSR_READ_1(sc, RE_MACDBG) & BIT_7)) {
ClearEthPhyOcpBit(sc, 0xA428, BIT_7);
ClearEthPhyOcpBit(sc, 0xA428, BIT_7);
SetEthPhyBit(sc, 0x14, BIT_7);