BIT_6
#define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */
#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
#define RB_WP_T_ON BIT_6 /* Write Pointer Test On */
#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6
#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-T Full Duplex */
#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
#define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */
#define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */
#define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */
#define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */
#define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */
#define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */
#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
#define PCI_EXT_PATCH_2 BIT_6
#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
#define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */
#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
#define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */
#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
#define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */
PhyRegValue &= ~(BIT_6);
PhyRegValue &= ~(BIT_6|BIT_7);
PhyRegValue &= BIT_6;
} while(PhyRegValue != BIT_6 && WaitCount < 1000);
if (PhyRegValue != BIT_6 && WaitCount == 1000) bSuccess = FALSE;
PhyRegValue &= BIT_6;
} while(PhyRegValue != BIT_6 && i < 1000);
if (PhyRegValue != BIT_6 && WaitCount == 1000) bSuccess = FALSE;
PhyRegValue &= BIT_6;
} while(PhyRegValue != BIT_6 && WaitCount < 1000);
if (PhyRegValue != BIT_6 && WaitCount == 1000) bSuccess = FALSE;
PhyRegValue &= BIT_6;
} while(PhyRegValue != BIT_6 && i < 1000);
if (PhyRegValue != BIT_6 && WaitCount == 1000) bSuccess = FALSE;
PhyRegValue &= ~(BIT_6);
PhyRegValue &= ~(BIT_6);
PhyRegValue &= ~(BIT_6);
PhyRegValue &= ~(BIT_6);
PhyRegValue &= ~(BIT_6);
SetEthPhyBit(sc, 0x11, BIT_6);
SetEthPhyBit(sc, 0x11, BIT_6);
SetEthPhyBit(sc, 0x11, BIT_6);
SetEthPhyBit(sc, 0x11, BIT_6);
SetEthPhyBit(sc, 0x11, BIT_6);
BIT_7|BIT_6|BIT_5,
BIT_6
BIT_7|BIT_6|BIT_5|BIT_4,
ClearEthPhyOcpBit(sc, 0xA432, BIT_6);
SetEthPhyOcpBit(sc, 0xA4CA, BIT_6);
ioffset_p1 = ((TmpUshort & (BIT_8|BIT_7|BIT_6|BIT_5))>>5);
CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) | (BIT_6|BIT_7));
SetPCIePhyBit(sc, 0x0B, (BIT_3 | BIT_6));
(BIT_4 | BIT_6)
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_6);
Data8 |= (BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
data16 &= ~(BIT_7 | BIT_6);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_6);
data16 &= ~(BIT_7 | BIT_6);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_6);
(BIT_13|BIT_12|BIT_10|BIT_9|BIT_8|BIT_7|BIT_6|BIT_4),
(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
data16 |= (BIT_6 | BIT_5 | BIT_4);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_6);
ClearPCIePhyBit(sc, 0x0C, (BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4));
BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5,
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_6);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
data16 |= (BIT_6 | BIT_5 | BIT_4);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
BIT_6,
BIT_6,
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_6);
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_6);
Data8 &= ~(BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
ClearPCIePhyBit(sc, 0x19, BIT_6);
ClearPCIePhyBit(sc, 0x59, BIT_6);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_6);
data16 &= ~(BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5);
data16 |= (BIT_6);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
SetMcuAccessRegBit(sc, 0xE052, (BIT_6|BIT_5|BIT_3));
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~BIT_6;
data16 |= BIT_6;
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) | BIT_6);
CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_6);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_6);
CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) & ~(BIT_6|BIT_7));
data |= (BIT_4 | BIT_5 | BIT_6);
data |= (BIT_4 | BIT_5 | BIT_6);
data |= (BIT_4 | BIT_5 | BIT_6);