BIT_5
#define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */
#define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */
#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
#define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */
#define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */
#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5
#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-T Half Duplex */
#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
#define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */
#define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */
#define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */
#define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */
#define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */
#define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/
#define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */
#define GMR_FS_MII_ERR BIT_5 /* MII Error */
#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5
#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
#define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */
#define PCI_EXT_PATCH_1 BIT_5
#define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
#define CS_STOP_DONE BIT_5 /* Stop Master is finished */
#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
#define Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */
#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */
#define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */
#define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */
if ((PhyRegValue & BIT_5) == 0)
if (PhyRegValue & BIT_5) {
if ((PhyRegValue& BIT_5) == 0)
if (PhyRegValue & BIT_5) {
MP_WritePhyUshort(sc, 0x14, MP_ReadPhyUshort(sc, 0x14) | BIT_5);
MP_WritePhyUshort(sc, 0x0d, MP_ReadPhyUshort(sc, 0x0d) | BIT_5);
MP_WritePhyUshort(sc, 0x14, MP_ReadPhyUshort(sc, 0x14) | BIT_5);
MP_WritePhyUshort(sc, 0x0D, MP_ReadPhyUshort(sc, 0x0D) & ~BIT_5);
MP_WritePhyUshort(sc, 0x14, MP_ReadPhyUshort(sc, 0x14) | BIT_5);
MP_WritePhyUshort(sc, 0x0D, MP_ReadPhyUshort(sc, 0x0D) & ~BIT_5);
MP_WritePhyUshort(sc, 0x0d, MP_ReadPhyUshort(sc, 0x0d) | BIT_5);
MP_WritePhyUshort(sc, 0x14, MP_ReadPhyUshort(sc, 0x14) | BIT_5);
MP_WritePhyUshort(sc, 0x0d, MP_ReadPhyUshort(sc, 0x0d) | BIT_5);
Data |= BIT_5;
PhyRegValue |= (BIT_5);
PhyRegValue |= (BIT_5);
PhyRegValue |= (BIT_5);
PhyRegValue |= (BIT_5);
BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0,
BIT_7|BIT_6|BIT_5,
BIT_7|BIT_6|BIT_5|BIT_4,
BIT_5|BIT_4
SetEthPhyOcpBit(sc, 0xA5D4, BIT_5);
ClearEthPhyOcpBit(sc, 0xBFA4, BIT_5);
#define ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE BIT_5
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5);
ioffset_p1 = ((TmpUshort & (BIT_8|BIT_7|BIT_6|BIT_5))>>5);
if ((MP_ReadMcuAccessRegWord(sc, 0xD442) & BIT_5) &&
BIT_5,
BIT_5
data16 |= (BIT_2 | BIT_5 | BIT_9);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5);
SetPCIePhyBit(sc, 0x19, BIT_5);
SetPCIePhyBit(sc, 0x0A, BIT_5);
SetPCIePhyBit(sc, 0x19, BIT_5);
SetPCIePhyBit(sc, 0x0A, BIT_5);
Data8 |= (BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
data16 |= BIT_5;
data16 |= (BIT_2 | BIT_5 | BIT_9);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
data16 |= BIT_5;
data16 |= (BIT_2 | BIT_5 | BIT_9);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5);
(BIT_11|BIT_5)
(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4),
(BIT_5 | BIT_11)
(BIT_5 | BIT_11)
ClearPCIePhyBit(sc, 0x19, (BIT_5 | BIT_0));
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
data16 |= (BIT_6 | BIT_5 | BIT_4);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
ClearPCIePhyBit(sc, 0x0C, (BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4));
BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5,
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
data16 |= (BIT_6 | BIT_5 | BIT_4);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5);
Data8 &= ~(BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
(BIT_5 | BIT_4),
BIT_5
(BIT_5 | BIT_4),
BIT_5
data16 &= ~(BIT_5 | BIT_4);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 |= (BIT_5 | BIT_4 | BIT_1 | BIT_0);
data16 &= ~(BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
data16 |= (BIT_4 | BIT_5);
SetMcuAccessRegBit(sc, 0xE052, (BIT_6|BIT_5|BIT_3));
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
CSR_WRITE_2(sc, 0x1880, CSR_READ_2(sc, 0x1880) & ~(BIT_4 | BIT_5));
data |= (BIT_4 | BIT_5 | BIT_6);
data |= (BIT_4 | BIT_5 | BIT_6);
data |= (BIT_4 | BIT_5 | BIT_6);