BIT_3
#define TXA_START_RC BIT_3 /* Start sync Rate Control */
#define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */
#define BMU_OP_ON BIT_3 /* BMU Operational On */
#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */
#define RB_PC_DEC BIT_3 /* Packet Counter Decrement */
#define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */
#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3
#define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */
#define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */
#define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */
#define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */
#define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */
#define GM_GPSR_PART_MODE BIT_3 /* Partition mode */
#define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */
#define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */
#define GMR_FS_FRAGMENT BIT_3 /* Fragment */
#define GMF_OPER_ON BIT_3 /* Operational Mode On */
#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */
#define Y2_ASF_RESET BIT_3 /* ASF system in reset state */
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */
#define GMC_PAUSE_ON BIT_3 /* Pause On */
#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */
#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
#define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
#define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */
#define CS_MRST_CLR BIT_3 /* Clear Master Reset */
#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */
#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */
#define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */
#define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */
SetEthPhyBit(sc, 0x11, (BIT_3 | BIT_2));
SetEthPhyBit(sc, 0x11, (BIT_3 | BIT_2));
dout_tapbin = ~(dout_tapbin^BIT_3);
BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0,
SetEthPhyOcpBit(sc, 0xBC08, (BIT_3 | BIT_2));
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_3);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) | BIT_3);
ClearEthPhyOcpBit(sc, 0xA468, BIT_3 | BIT_1);
SetPCIePhyBit(sc, 0x0B, (BIT_3 | BIT_6));
CSR_WRITE_1(sc, 0x1A, CSR_READ_1(sc, 0x1A) & ~(BIT_2 |BIT_3));
SetPCIePhyBit(sc, 0x00, BIT_3);
Data8 |= (BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
SetPCIePhyBit(sc, 0x00, BIT_3);
SetPCIePhyBit(sc, 0x00, BIT_3);
data16 &= ~(BIT_3 | BIT_2 | BIT_1);
Data32 |= (BIT_2| BIT_3 | BIT_4);
ClearPCIePhyBit(sc, 0x00, BIT_3);
SetPCIePhyBit(sc, 0x00, (BIT_3));
ClearPCIePhyBit(sc, 0x00, BIT_3);
ClearPCIePhyBit(sc, 0x00, BIT_3);
data16 |= BIT_3;
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_3);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_3);
data16 &= ~(BIT_3 | BIT_0);
data16 |= BIT_3;
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_3 | BIT_2 | BIT_1);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_3);
Data8 &= ~(BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7);
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_3);
data16 |= (BIT_3|BIT_2);
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 &= ~(BIT_14 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
SetMcuAccessRegBit(sc, 0xE052, (BIT_6|BIT_5|BIT_3));
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);