BIT_13
#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */
#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
#define WOL_CTL_PATTERN_OCC BIT_13
#define PHY_M_AN_RF BIT_13 /* Remote Fault */
#define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */
#define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */
#define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */
#define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */
#define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */
#define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */
#define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */
#define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */
#define GMR_FS_VLAN BIT_13 /* VLAN Packet */
#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */
#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
#define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */
#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
#define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */
#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */
data = MP_ReadPhyUshort(sc, 0x11) & ~(BIT_12 | BIT_13 | BIT_14);
ClearEthPhyOcpBit(sc, 0xA442, BIT_12 | BIT_13);
PhyRegValue &= ~(BIT_12 | BIT_13 | BIT_14 | BIT_15);
ClearEthPhyBit(sc, 0x14, (BIT_14 | BIT_13));
BIT_13,
ClearEthPhyBit(sc, 0x14, (BIT_14 | BIT_13));
BIT_13,
ClearEthPhyBit(sc, 0x14, (BIT_14 | BIT_13));
ClearEthPhyBit(sc, 0x14, (BIT_14 | BIT_13));
BIT_13,
ClearEthPhyBit(sc, 0x14, (BIT_14 | BIT_13));
BIT_13,
BIT_15|BIT_14|BIT_13|BIT_12,
BIT_15|BIT_14|BIT_13|BIT_12,
BIT_15|BIT_14|BIT_13|BIT_12,
BIT_15|BIT_14|BIT_13|BIT_12,
(BIT_13 | BIT_12),
ClearEthPhyBit(sc, 0x14, (BIT_13 | BIT_12));
ClearEthPhyBit(sc, 0x14, (BIT_13 | BIT_12));
ClearEthPhyBit(sc, 0x14, (BIT_13 | BIT_12));
ClearEthPhyBit(sc, 0x14, (BIT_13 | BIT_12));
ClearEthPhyBit(sc, 0x14, (BIT_13 | BIT_12));
ClearEthPhyBit(sc, 0x14, (BIT_13 | BIT_12));
ClearEthPhyBit(sc, 0x14, (BIT_13 | BIT_12));
BIT_15|BIT_14|BIT_13|BIT_12|BIT_11|BIT_10|BIT_8,
BIT_15|BIT_14|BIT_13|BIT_12,
BIT_15|BIT_14|BIT_13|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_15|BIT_14|BIT_13|BIT_12|BIT_11,
BIT_15|BIT_13|BIT_12);
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_15|BIT_14|BIT_13|BIT_12|BIT_11,
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_15|BIT_14|BIT_13|BIT_12,
BIT_14|BIT_13|BIT_12
SetEthPhyOcpBit(sc, 0xD068, BIT_13);
BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8,
ioffset_p3 |= ((TmpUshort & (BIT_15 | BIT_14 | BIT_13))>>13);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
SetPCIePhyBit(sc, 0x1E, BIT_13);
SetPCIePhyBit(sc, 0x05, BIT_13);
SetPCIePhyBit(sc, 0x1E, BIT_13);
SetPCIePhyBit(sc, 0x05, BIT_13);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
(BIT_13|BIT_12|BIT_10|BIT_9|BIT_8|BIT_7|BIT_6|BIT_4),
(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
(BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
SetPCIePhyBit(sc, 0x1E, BIT_13);
data16 &= ~(BIT_14 | BIT_13);
ClearPCIePhyBit(sc, 0x0C, (BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4));
BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5,
(BIT_14 | BIT_13 | BIT_12),
(BIT_13 | BIT_12)
ClearPCIePhyBit(sc, 0x1B, (BIT_14 | BIT_13 | BIT_12));
(BIT_14 | BIT_13 | BIT_12),
(BIT_13 | BIT_12)
ClearPCIePhyBit(sc, 0x5B, (BIT_14 | BIT_13 | BIT_12));
data |= BIT_13;
data = MP_ReadPhyUshort(sc, 0x11) | BIT_13 | BIT_14;
ClearEthPhyOcpBit(sc, 0xA442, BIT_12 | BIT_13);
data &= ~BIT_13;