BIT_11
#define GLB_GPIO_TEST_SEL_BASE BIT_11
#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */
#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11
#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
#define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */
#define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */
#define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */
#define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */
#define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */
#define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */
#define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */
#define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */
#define GM_GPSR_PAUSE BIT_11 /* Pause State */
#define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */
#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */
#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */
#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */
#define PCI_PATCH_DIR_3 BIT_11
#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */
#define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */
#define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */
#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */
PhyRegValue &= ~(BIT_11);
PhyRegValue &= ~(BIT_11);
PhyRegValue |= (BIT_11|BIT_12);
PhyRegValue &= ~(BIT_11|BIT_12);
PhyRegValue |= (BIT_11);
if (PhyRegValue & BIT_11) {
if ((PhyRegValue & BIT_11) == 0x0000) {
if (PhyRegValue & BIT_11)
PhyRegValue |= BIT_11;
BIT_11 | BIT_10,
BIT_11);
BIT_11 | BIT_10 | BIT_9 | BIT_8,
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
Data &= ~BIT_11;
SetEthPhyBit(sc, 0x14, BIT_11);
SetEthPhyBit(sc, 0x11, BIT_11);
SetEthPhyBit(sc, 0x14, BIT_11);
SetEthPhyBit(sc, 0x11, BIT_11);
BIT_15|BIT_14|BIT_13|BIT_12|BIT_11|BIT_10|BIT_8,
BIT_11|BIT_10|BIT_9|BIT_8);
BIT_15|BIT_14|BIT_13|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_15|BIT_14|BIT_13|BIT_12|BIT_11,
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_15|BIT_14|BIT_13|BIT_12|BIT_11,
BIT_15|BIT_12|BIT_11);
BIT_13|BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
BIT_12|BIT_11|BIT_10|BIT_9|BIT_8,
SetEthPhyBit(sc, 0x14, BIT_11);
SetEthPhyBit( sc, 0x11, BIT_11 );
BIT_11|BIT_10|BIT_9,
BIT_11|BIT_9
SetEthPhyOcpBit(sc, 0xA442, BIT_11);
SetEthPhyOcpBit(sc, 0xA442, BIT_11);
SetEthPhyOcpBit(sc, 0xA442, BIT_11);
SetEthPhyOcpBit(sc, 0xA442, BIT_11);
BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8,
BIT_11
if (OCP_read(sc, reg, 2) & BIT_11)
if ((OCP_read(sc, reg, 4) & BIT_11) == 0)
if (CSR_READ_4(sc, RE_TXCFG) & BIT_11)
ioffset_p2 = ((TmpUshort & (BIT_12|BIT_11|BIT_10|BIT_9))>>9);
Data32 |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
Data32 |= BIT_11 | BIT_10;
Data32 |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
Data32 |= BIT_11 | BIT_10;
(BIT_13|BIT_12|BIT_11|BIT_10|BIT_8|BIT_7|BIT_6|BIT_5|BIT_4),
Data32 |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
Data32 |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
(BIT_11|BIT_5)
(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4),
(BIT_5 | BIT_11)
(BIT_5 | BIT_11)
ClearPCIePhyBit(sc, 0x1E, BIT_11);
SetPCIePhyBit(sc, 0x1D, BIT_11);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
Data32 |= BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12;
ClearPCIePhyBit(sc, 0x0C, (BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4));
BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5,
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
Data32 |= BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12;
ClearPCIePhyBit(sc, 0x24, BIT_11);
ClearPCIePhyBit(sc, 0x64, BIT_11);
SetPCIePhyBit(sc, 0x1B, (BIT_11 | BIT_10 | BIT_9));
SetPCIePhyBit(sc, 0x5B, (BIT_11 | BIT_10 | BIT_9));
data16 &= ~(BIT_11 | BIT_10);
data16 &= ~(BIT_14 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
data16 |= (BIT_8|BIT_9|BIT_10|BIT_11|BIT_12);
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
while (!(CSR_READ_4(sc,RE_TXCFG) & BIT_11)) DELAY(100);