Symbol: BIT_0
sys/dev/netif/msk/if_mskreg.h
1020
#define I2C_STOP BIT_0 /* Interrupt I2C transfer */
sys/dev/netif/msk/if_mskreg.h
1023
#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
sys/dev/netif/msk/if_mskreg.h
1028
#define I2C_CLK BIT_0 /* I2C Clock Port */
sys/dev/netif/msk/if_mskreg.h
1036
#define BSC_STOP BIT_0 /* Stop Blink Source Counter */
sys/dev/netif/msk/if_mskreg.h
1039
#define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */
sys/dev/netif/msk/if_mskreg.h
1044
#define BSC_T_STEP BIT_0 /* Test step */
sys/dev/netif/msk/if_mskreg.h
1058
#define RI_RST_SET BIT_0 /* Set RAM Interface Reset */
sys/dev/netif/msk/if_mskreg.h
1077
#define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */
sys/dev/netif/msk/if_mskreg.h
1085
#define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */
sys/dev/netif/msk/if_mskreg.h
1088
#define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */
sys/dev/netif/msk/if_mskreg.h
1113
#define BMU_RST_SET BIT_0 /* Set BMU Reset */
sys/dev/netif/msk/if_mskreg.h
1143
#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
sys/dev/netif/msk/if_mskreg.h
1162
#define RB_PC_INC BIT_0 /* Packet Counter Increment */
sys/dev/netif/msk/if_mskreg.h
1170
#define RB_RP_INC BIT_0 /* Read Pointer Increment */
sys/dev/netif/msk/if_mskreg.h
1178
#define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */
sys/dev/netif/msk/if_mskreg.h
1235
#define WOL_CTL_DIS_PATTERN_UNIT BIT_0
sys/dev/netif/msk/if_mskreg.h
1246
#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
sys/dev/netif/msk/if_mskreg.h
1386
#define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */
sys/dev/netif/msk/if_mskreg.h
1434
#define PHY_M_PS_JABBER BIT_0 /* Jabber */
sys/dev/netif/msk/if_mskreg.h
1458
#define PHY_M_IS_JABBER BIT_0 /* Jabber */
sys/dev/netif/msk/if_mskreg.h
1480
#define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */
sys/dev/netif/msk/if_mskreg.h
1510
#define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */
sys/dev/netif/msk/if_mskreg.h
1511
#define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */
sys/dev/netif/msk/if_mskreg.h
1611
#define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
sys/dev/netif/msk/if_mskreg.h
1829
#define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
sys/dev/netif/msk/if_mskreg.h
1911
#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
sys/dev/netif/msk/if_mskreg.h
1969
#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
sys/dev/netif/msk/if_mskreg.h
1996
#define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */
sys/dev/netif/msk/if_mskreg.h
2004
#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
sys/dev/netif/msk/if_mskreg.h
2012
#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */
sys/dev/netif/msk/if_mskreg.h
2034
#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0
sys/dev/netif/msk/if_mskreg.h
2037
#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0
sys/dev/netif/msk/if_mskreg.h
2042
#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
sys/dev/netif/msk/if_mskreg.h
2049
#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
sys/dev/netif/msk/if_mskreg.h
2067
#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
sys/dev/netif/msk/if_mskreg.h
2092
#define GPC_RST_SET BIT_0 /* Set GPHY Reset */
sys/dev/netif/msk/if_mskreg.h
2101
#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
sys/dev/netif/msk/if_mskreg.h
2107
#define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */
sys/dev/netif/msk/if_mskreg.h
306
#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
sys/dev/netif/msk/if_mskreg.h
338
#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
sys/dev/netif/msk/if_mskreg.h
371
#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
sys/dev/netif/msk/if_mskreg.h
388
#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
sys/dev/netif/msk/if_mskreg.h
401
#define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */
sys/dev/netif/msk/if_mskreg.h
801
#define CS_RST_SET BIT_0 /* Set Software Reset */
sys/dev/netif/msk/if_mskreg.h
804
#define LED_STAT_OFF BIT_0 /* Status LED Off */
sys/dev/netif/msk/if_mskreg.h
814
#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
sys/dev/netif/msk/if_mskreg.h
844
#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
sys/dev/netif/msk/if_mskreg.h
877
#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
sys/dev/netif/msk/if_mskreg.h
891
#define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
sys/dev/netif/msk/if_mskreg.h
938
#define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */
sys/dev/netif/msk/if_mskreg.h
943
#define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */
sys/dev/netif/msk/if_mskreg.h
961
#define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */
sys/dev/netif/msk/if_mskreg.h
967
#define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */
sys/dev/netif/msk/if_mskreg.h
974
#define TIM_T_STEP BIT_0 /* Test step */
sys/dev/netif/msk/if_mskreg.h
982
#define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */
sys/dev/netif/msk/if_mskreg.h
992
#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */
sys/dev/netif/re/re.c
10006
data &= ~(BIT_1 | BIT_0);
sys/dev/netif/re/re.c
10018
ClearMcuAccessRegBit(sc, 0xE040, (BIT_1|BIT_0));
sys/dev/netif/re/re.c
10023
ClearEthPhyOcpBit(sc, 0xA6D4, BIT_0);
sys/dev/netif/re/re.c
10032
ClearMcuAccessRegBit(sc, 0xE040, (BIT_1|BIT_0));
sys/dev/netif/re/re.c
10035
ClearEthPhyOcpBit(sc, 0xA6D4, BIT_0);
sys/dev/netif/re/re.c
10088
data &= ~(BIT_0);
sys/dev/netif/re/re.c
10104
data &= ~(BIT_0);
sys/dev/netif/re/re.c
10110
data &= ~(BIT_0);
sys/dev/netif/re/re.c
10126
ClearMcuAccessRegBit(sc, 0xE052, BIT_0);
sys/dev/netif/re/re.c
10254
TmpUshort |= BIT_0;
sys/dev/netif/re/re.c
10407
ClearEthPhyOcpBit(sc, 0xB82E, BIT_0);
sys/dev/netif/re/re.c
1150
CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) & ~BIT_0);
sys/dev/netif/re/re.c
11916
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
11919
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
11932
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
13296
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
13299
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
13353
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
14719
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
14722
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
14736
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
14761
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
17252
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
17256
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
17291
PhyRegValue &= ~BIT_0;
sys/dev/netif/re/re.c
17302
PhyRegValue &= ~BIT_0;
sys/dev/netif/re/re.c
17332
if ((MP_ReadPhyUshort(sc, 0x17) & BIT_0) == 0)
sys/dev/netif/re/re.c
18233
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
18237
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
18254
PhyRegValue &= ~BIT_0;
sys/dev/netif/re/re.c
18301
if (!(PhyRegValue & BIT_0))
sys/dev/netif/re/re.c
19125
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
19129
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
19159
PhyRegValue &= ~BIT_0;
sys/dev/netif/re/re.c
19197
if (!(PhyRegValue & BIT_0))
sys/dev/netif/re/re.c
19498
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
19502
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
19524
PhyRegValue &= ~BIT_0;
sys/dev/netif/re/re.c
19560
if (!(PhyRegValue & BIT_0))
sys/dev/netif/re/re.c
20071
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
20075
PhyRegValue |= BIT_0;
sys/dev/netif/re/re.c
20101
PhyRegValue &= ~BIT_0;
sys/dev/netif/re/re.c
21212
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
21270
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
21337
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
21679
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
22673
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
22731
PhyRegValue &= ~(BIT_0);
sys/dev/netif/re/re.c
25058
PhyRegValue &= (BIT_1 | BIT_0);
sys/dev/netif/re/re.c
25117
CSR_WRITE_1(sc, 0x82, CSR_READ_1(sc, 0x82)|BIT_0);
sys/dev/netif/re/re.c
25390
MP_WritePhyUshort(sc, 0x16, MP_ReadPhyUshort(sc, 0x16) | BIT_0);
sys/dev/netif/re/re.c
25428
MP_WritePhyUshort(sc, 0x16, MP_ReadPhyUshort(sc, 0x16) | BIT_0);
sys/dev/netif/re/re.c
25505
MP_WritePhyUshort(sc, 0x16, MP_ReadPhyUshort(sc, 0x16) | BIT_0);
sys/dev/netif/re/re.c
26570
Data |= BIT_0;
sys/dev/netif/re/re.c
26677
Data &= ~BIT_0;
sys/dev/netif/re/re.c
26717
Data |= BIT_0;
sys/dev/netif/re/re.c
26772
Data &= ~BIT_0;
sys/dev/netif/re/re.c
27393
Data |= BIT_0;
sys/dev/netif/re/re.c
27473
Data &= ~BIT_0;
sys/dev/netif/re/re.c
27500
Data |= BIT_0;
sys/dev/netif/re/re.c
27544
Data &= ~BIT_0;
sys/dev/netif/re/re.c
27576
Data |= BIT_0;
sys/dev/netif/re/re.c
27656
Data &= ~BIT_0;
sys/dev/netif/re/re.c
28635
SetEthPhyBit(sc, 0x10, BIT_0);
sys/dev/netif/re/re.c
28701
SetEthPhyBit(sc, 0x10, BIT_0);
sys/dev/netif/re/re.c
28745
SetEthPhyBit(sc, 0x10, BIT_0);
sys/dev/netif/re/re.c
29081
SetEthPhyBit(sc, 0x10, BIT_0);
sys/dev/netif/re/re.c
29129
SetEthPhyBit(sc, 0x10, BIT_0);
sys/dev/netif/re/re.c
29502
TmpUshort &= (BIT_1|BIT_0);
sys/dev/netif/re/re.c
29611
BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0,
sys/dev/netif/re/re.c
29993
BIT_1|BIT_0,
sys/dev/netif/re/re.c
30003
BIT_2|BIT_1|BIT_0,
sys/dev/netif/re/re.c
30010
BIT_2|BIT_1|BIT_0,
sys/dev/netif/re/re.c
30096
ClearEthPhyOcpBit(sc, 0xB896, BIT_0);
sys/dev/netif/re/re.c
30149
SetEthPhyOcpBit(sc, 0xB896, BIT_0);
sys/dev/netif/re/re.c
30165
ClearEthPhyOcpBit(sc, 0xA454, BIT_0);
sys/dev/netif/re/re.c
30170
ClearEthPhyOcpBit(sc, 0xA86A, BIT_0);
sys/dev/netif/re/re.c
30598
ClearEthPhyOcpBit(sc, 0xB896, BIT_0);
sys/dev/netif/re/re.c
30616
SetEthPhyOcpBit(sc, 0xB896, BIT_0);
sys/dev/netif/re/re.c
30621
SetEthPhyOcpBit(sc, 0xA86A, BIT_0);
sys/dev/netif/re/re.c
30622
SetEthPhyOcpBit(sc, 0xA6F0, BIT_0);
sys/dev/netif/re/re.c
31573
OCP_write(sc, ocp_reg_mutex_ib, 1, BIT_0);
sys/dev/netif/re/re.c
31590
OCP_write(sc, ocp_reg_mutex_ib, 1, BIT_0);
sys/dev/netif/re/re.c
31634
OCP_write(sc, ocp_reg_mutex_prio, 1, BIT_0);
sys/dev/netif/re/re.c
31652
if (OCP_read(sc, 0x128, 1) & BIT_0)
sys/dev/netif/re/re.c
31701
tmp_value |= BIT_0;
sys/dev/netif/re/re.c
31738
tmp_value |= BIT_0;
sys/dev/netif/re/re.c
3454
RE_CMAC_WRITE_1(sc, RE_CMAC_IBCR2, RE_CMAC_READ_1(sc, RE_CMAC_IBCR2) & ~(BIT_0));
sys/dev/netif/re/re.c
3479
RE_CMAC_WRITE_1(sc, RE_CMAC_IBCR0, RE_CMAC_READ_1(sc, RE_CMAC_IBCR0) & ~(BIT_0));
sys/dev/netif/re/re.c
3553
SetMcuAccessRegBit(sc, 0xC0B6, BIT_0);
sys/dev/netif/re/re.c
3566
ClearMcuAccessRegBit(sc, 0xC0B6, BIT_0);
sys/dev/netif/re/re.c
3659
if ((CSR_READ_2(sc, RE_IntrMitigate) & (BIT_0 | BIT_1 | BIT_8)) == (BIT_0 | BIT_1 | BIT_8))
sys/dev/netif/re/re.c
3803
CSR_WRITE_1(sc, 0xF4, CSR_READ_1(sc, 0xF4) & ~(BIT_0|BIT_1));
sys/dev/netif/re/re.c
3815
CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~(BIT_0|BIT_1|BIT_2));
sys/dev/netif/re/re.c
3880
CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) & ~BIT_0);
sys/dev/netif/re/re.c
4457
if (!(CmacMemPhysAddress & BIT_0)) {
sys/dev/netif/re/re.c
4568
ioffset_p0 |= (TmpUshort & (BIT_2| BIT_1 | BIT_0));
sys/dev/netif/re/re.c
538
ClearEthPhyOcpBit(sc, 0xA466, BIT_0);
sys/dev/netif/re/re.c
554
return (MP_ReadMcuAccessRegWord(sc, 0xD408) & BIT_0);
sys/dev/netif/re/re.c
568
MP_WriteMcuAccessRegWord(sc, 0xD408, MP_ReadMcuAccessRegWord(sc, 0xD408) & ~(BIT_0));
sys/dev/netif/re/re.c
5688
CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) & ~BIT_0);
sys/dev/netif/re/re.c
5719
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
5734
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
5741
CSR_WRITE_1(sc, RE_CFG4, CSR_READ_1(sc, RE_CFG4) | BIT_0);
sys/dev/netif/re/re.c
5747
CSR_WRITE_1(sc, RE_CFG4, CSR_READ_1(sc, RE_CFG4) & ~ BIT_0);
sys/dev/netif/re/re.c
5770
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
5812
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
5945
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
5991
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6069
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6136
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6244
Data32 &= ~BIT_0;
sys/dev/netif/re/re.c
6246
Data32 |= BIT_0;
sys/dev/netif/re/re.c
6297
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6323
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6338
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6346
SetPCIePhyBit(sc, 0x03, BIT_0);
sys/dev/netif/re/re.c
6357
SetPCIePhyBit(sc, 0x03, BIT_0);
sys/dev/netif/re/re.c
6375
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6403
Data32 &= ~BIT_0;
sys/dev/netif/re/re.c
6405
Data32 |= BIT_0;
sys/dev/netif/re/re.c
6429
data16 &= ~BIT_0;
sys/dev/netif/re/re.c
6449
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6490
Data32 &= ~BIT_0;
sys/dev/netif/re/re.c
6492
Data32 |= BIT_0;
sys/dev/netif/re/re.c
6531
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6558
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6569
MP_WriteMcuAccessRegWord(sc, 0xD400, MP_ReadMcuAccessRegWord(sc, 0xD400) & ~(BIT_0));
sys/dev/netif/re/re.c
6574
data16 |= (BIT_0);
sys/dev/netif/re/re.c
6576
data16 &= ~(BIT_0);
sys/dev/netif/re/re.c
6629
Data32 &= ~BIT_0;
sys/dev/netif/re/re.c
6631
Data32 |= BIT_0;
sys/dev/netif/re/re.c
6635
Data32 &= ~(BIT_0 | BIT_1 | BIT_2);
sys/dev/netif/re/re.c
6636
Data32 |= (BIT_0);
sys/dev/netif/re/re.c
6656
SetPCIePhyBit(sc, 0x1E, BIT_0);
sys/dev/netif/re/re.c
6673
SetPCIePhyBit(sc, 0x1E, BIT_0);
sys/dev/netif/re/re.c
6691
SetPCIePhyBit(sc, 0x1E, BIT_0);
sys/dev/netif/re/re.c
6694
ClearPCIePhyBit(sc, 0x19, (BIT_5 | BIT_0));
sys/dev/netif/re/re.c
6708
SetPCIePhyBit(sc, 0x1E, BIT_0);
sys/dev/netif/re/re.c
6729
data16 |= (BIT_0);
sys/dev/netif/re/re.c
6751
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
6756
data16 &= ~(BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
6761
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6818
Data32 &= ~BIT_0;
sys/dev/netif/re/re.c
6820
Data32 |= BIT_0;
sys/dev/netif/re/re.c
6824
Data32 &= ~(BIT_0 | BIT_1 | BIT_2);
sys/dev/netif/re/re.c
6825
Data32 |= (BIT_0 | BIT_1);
sys/dev/netif/re/re.c
6853
ClearPCIePhyBit(sc, 0x0B, BIT_0);
sys/dev/netif/re/re.c
6862
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
6904
MP_WriteMcuAccessRegWord(sc, 0xD400, MP_ReadMcuAccessRegWord(sc, 0xD400) & ~(BIT_0));
sys/dev/netif/re/re.c
6925
data16 &= ~(BIT_3 | BIT_0);
sys/dev/netif/re/re.c
6927
data16 |= BIT_0;
sys/dev/netif/re/re.c
6935
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
6944
data16 |= (BIT_0);
sys/dev/netif/re/re.c
6946
data16 &= ~(BIT_0);
sys/dev/netif/re/re.c
6981
Data32 &= ~BIT_0;
sys/dev/netif/re/re.c
6983
Data32 |= BIT_0;
sys/dev/netif/re/re.c
6987
Data32 &= ~(BIT_0 | BIT_1);
sys/dev/netif/re/re.c
6988
Data32 |= (BIT_0);
sys/dev/netif/re/re.c
7020
ClearPCIePhyBit(sc, 0x0B, BIT_0);
sys/dev/netif/re/re.c
7022
CSR_WRITE_1(sc, RE_CFG3, CSR_READ_1(sc, RE_CFG3) & ~BIT_0);
sys/dev/netif/re/re.c
7107
CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) | BIT_0);
sys/dev/netif/re/re.c
7250
CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) & ~BIT_0);
sys/dev/netif/re/re.c
7406
data16 &= ~(BIT_0);
sys/dev/netif/re/re.c
7414
if (sc->re_dash && !(MP_ReadByteFun0PciEConfigSpace(sc, 0x79) & BIT_0))
sys/dev/netif/re/re.c
7437
data16 &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
7438
data16 |= (BIT_5 | BIT_4 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
7458
data16 &= ~(BIT_1 | BIT_0);
sys/dev/netif/re/re.c
7459
data16 |= (BIT_0);
sys/dev/netif/re/re.c
7463
data16 &= ~(BIT_14 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
7464
data16 |= (BIT_14 | BIT_10 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
7476
data16 &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
sys/dev/netif/re/re.c
7491
CSR_WRITE_1(sc, 0xD3, CSR_READ_1(sc, 0xD3) | BIT_0);
sys/dev/netif/re/re.c
7499
SetMcuAccessRegBit(sc, 0xEB54, BIT_0);
sys/dev/netif/re/re.c
7501
ClearMcuAccessRegBit(sc, 0xEB54, BIT_0);
sys/dev/netif/re/re.c
7516
CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) | BIT_0);
sys/dev/netif/re/re.c
9336
ClearEthPhyOcpBit(sc, 0xA5EA, BIT_0);
sys/dev/netif/re/re.c
9634
data |= BIT_1 | BIT_0;
sys/dev/netif/re/re.c
9670
data |= BIT_1 | BIT_0;
sys/dev/netif/re/re.c
9682
SetMcuAccessRegBit(sc, 0xE040, (BIT_1|BIT_0));
sys/dev/netif/re/re.c
9687
ClearEthPhyOcpBit(sc, 0xA6D4, BIT_0);
sys/dev/netif/re/re.c
9696
SetMcuAccessRegBit(sc, 0xE040, (BIT_1|BIT_0));
sys/dev/netif/re/re.c
9699
ClearEthPhyOcpBit(sc, 0xA6D4, BIT_0);
sys/dev/netif/re/re.c
9761
data |= BIT_0;
sys/dev/netif/re/re.c
9788
data &= ~BIT_0;
sys/dev/netif/re/re.c
9801
data &= ~BIT_0;
sys/dev/netif/re/re.c
9812
data |= BIT_0;
sys/dev/netif/re/re.c
9828
ClearMcuAccessRegBit(sc, 0xE052, BIT_0);
sys/dev/netif/re/re.c
9969
data &= ~(BIT_1 | BIT_0);