__u32
formats_size = sizeof(__u32) * plane->format_count;
__u32 weight;
__u32 handle;
__u32 _pad;
__u32 operation;
__u32 list_handle;
__u32 bo_number;
__u32 bo_info_size;
__u32 bo_handle;
__u32 bo_priority;
__u32 list_handle;
__u32 _pad;
__u32 op;
__u32 flags;
__u32 ctx_id;
__u32 ctx_id;
__u32 _pad;
__u32 hangs;
__u32 reset_status;
__u32 op;
__u32 flags;
__u32 op;
__u32 fd;
__u32 flags;
__u32 flags;
__u32 handle;
__u32 handle;
__u32 op;
__u32 data_size_bytes;
__u32 data[64];
__u32 handle;
__u32 _pad;
__u32 handle;
__u32 flags;
__u32 status;
__u32 domain;
__u32 ip_type;
__u32 ip_instance;
__u32 ring;
__u32 ctx_id;
__u32 ctx_id;
__u32 ip_type;
__u32 ip_instance;
__u32 ring;
__u32 fence_count;
__u32 wait_all;
__u32 status;
__u32 first_signaled;
__u32 handle;
__u32 op;
__u32 handle;
__u32 _pad;
__u32 operation;
__u32 flags;
__u32 chunk_id;
__u32 length_dw;
__u32 ctx_id;
__u32 bo_list_handle;
__u32 num_chunks;
__u32 _pad;
__u32 _pad;
__u32 flags;
__u32 ib_bytes;
__u32 ip_type;
__u32 ip_instance;
__u32 ring;
__u32 ip_type;
__u32 ip_instance;
__u32 ring;
__u32 ctx_id;
__u32 handle;
__u32 offset;
__u32 handle;
__u32 what;
__u32 pad;
__u32 handle;
__u32 fw_type;
__u32 ip_instance;
__u32 index;
__u32 _pad;
__u32 return_size;
__u32 query;
__u32 id;
__u32 _pad;
__u32 type;
__u32 ip_instance;
__u32 dword_offset;
__u32 count;
__u32 instance;
__u32 flags;
__u32 type;
__u32 offset;
__u32 type;
__u32 gds_gfx_partition_size;
__u32 compute_partition_size;
__u32 gds_total_size;
__u32 gws_per_gfx_partition;
__u32 gws_per_compute_partition;
__u32 oa_per_gfx_partition;
__u32 oa_per_compute_partition;
__u32 _pad;
__u32 ver;
__u32 feature;
__u32 device_id;
__u32 chip_rev;
__u32 external_rev;
__u32 pci_rev;
__u32 family;
__u32 num_shader_engines;
__u32 num_shader_arrays_per_engine;
__u32 gpu_counter_freq;
__u32 cu_active_number;
__u32 cu_ao_mask;
__u32 cu_bitmap[4][4];
__u32 enabled_rb_pipes_mask;
__u32 num_rb_pipes;
__u32 num_hw_gfx_contexts;
__u32 _pad;
__u32 virtual_address_alignment;
__u32 pte_fragment_size;
__u32 gart_page_size;
__u32 ce_ram_size;
__u32 vram_type;
__u32 vram_bit_width;
__u32 vce_harvest_config;
__u32 gc_double_offchip_lds_buf;
__u32 prim_buf_size;
__u32 pos_buf_size;
__u32 cntl_sb_buf_size;
__u32 param_buf_size;
__u32 wave_front_size;
__u32 num_shader_visible_vgprs;
__u32 num_cu_per_sh;
__u32 num_tcc_blocks;
__u32 gs_vgt_table_depth;
__u32 gs_prim_buffer_depth;
__u32 max_gs_waves_per_vgt;
__u32 _pad1;
__u32 cu_ao_bitmap[4][4];
__u32 hw_ip_version_major;
__u32 hw_ip_version_minor;
__u32 ib_start_alignment;
__u32 ib_size_alignment;
__u32 available_rings;
__u32 _pad;
__u32 uvd_max_handles;
__u32 uvd_used_handles;
__u32 sclk;
__u32 mclk;
__u32 eclk;
__u32 pad;
__u32 num_valid_entries;
__u32 pad;
__u32 crtc;
__u32 cmd;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 name;
__u32 name;
__u32 handle;
__u32 handle;
__u32 flags;
__u32 handle;
__u32 flags;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 flags;
__u32 pad;
__u32 count_handles;
__u32 flags;
__u32 first_signaled; /* only valid when not waiting all */
__u32 pad;
__u32 count_handles;
__u32 pad;
__u32 crtc_id; /* requested crtc_id */
__u32 active; /* return: crtc output is active */
__u32 crtc_id;
__u32 flags;
__u32 type;
__u32 length;
__u32 tv_sec;
__u32 tv_usec;
__u32 sequence;
__u32 crtc_id; /* 0 on older kernels that do not support this */
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
((__u32)(c) << 16) | ((__u32)(d) << 24))
__u32 clock;
__u32 vrefresh;
__u32 flags;
__u32 type;
__u32 count_fbs;
__u32 count_crtcs;
__u32 count_connectors;
__u32 count_encoders;
__u32 min_width;
__u32 max_width;
__u32 min_height;
__u32 max_height;
__u32 count_connectors;
__u32 crtc_id; /**< Id */
__u32 fb_id; /**< Id of framebuffer */
__u32 x; /**< x Position on the framebuffer */
__u32 y; /**< y Position on the framebuffer */
__u32 gamma_size;
__u32 mode_valid;
__u32 plane_id;
__u32 crtc_id;
__u32 fb_id; /* fb object contains surface format type */
__u32 flags; /* see above flags */
__u32 crtc_w;
__u32 crtc_h;
__u32 src_x;
__u32 src_y;
__u32 src_h;
__u32 src_w;
__u32 plane_id;
__u32 crtc_id;
__u32 fb_id;
__u32 possible_crtcs;
__u32 gamma_size;
__u32 count_format_types;
__u32 count_planes;
__u32 encoder_id;
__u32 encoder_type;
__u32 crtc_id; /**< Id of crtc */
__u32 possible_crtcs;
__u32 possible_clones;
__u32 count_modes;
__u32 count_props;
__u32 count_encoders;
__u32 encoder_id; /**< Current Encoder */
__u32 connector_id; /**< Id */
__u32 connector_type;
__u32 connector_type_id;
__u32 connection;
__u32 mm_width; /**< width in millimeters */
__u32 mm_height; /**< height in millimeters */
__u32 subpixel;
__u32 pad;
__u32 prop_id;
__u32 flags;
__u32 count_values;
__u32 count_enum_blobs;
__u32 prop_id;
__u32 connector_id;
__u32 count_props;
__u32 obj_id;
__u32 obj_type;
__u32 prop_id;
__u32 obj_id;
__u32 obj_type;
__u32 blob_id;
__u32 length;
__u32 fb_id;
__u32 width;
__u32 height;
__u32 pitch;
__u32 bpp;
__u32 depth;
__u32 handle;
__u32 fb_id;
__u32 width;
__u32 height;
__u32 pixel_format; /* fourcc code from drm_fourcc.h */
__u32 flags; /* see above flags */
__u32 handles[4];
__u32 pitches[4]; /* pitch for each plane */
__u32 offsets[4]; /* offset of each plane */
__u32 fb_id;
__u32 flags;
__u32 color;
__u32 num_clips;
__u32 connector_id;
__u32 flags;
__u32 crtc_id;
__u32 width;
__u32 height;
__u32 handle;
__u32 flags;
__u32 crtc_id;
__u32 width;
__u32 height;
__u32 handle;
__u32 crtc_id;
__u32 gamma_size;
__u32 crtc_id;
__u32 fb_id;
__u32 flags;
__u32 reserved;
__u32 crtc_id;
__u32 fb_id;
__u32 flags;
__u32 sequence;
__u32 height;
__u32 width;
__u32 bpp;
__u32 flags;
__u32 handle;
__u32 pitch;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 flags;
__u32 count_objs;
__u32 version;
__u32 flags;
__u32 count_formats;
__u32 formats_offset;
__u32 count_modifiers;
__u32 modifiers_offset;
__u32 offset;
__u32 pad;
__u32 length;
__u32 blob_id;
__u32 blob_id;
__u32 object_count;
__u32 flags;
__u32 lessee_id;
__u32 fd;
__u32 count_lessees;
__u32 pad;
__u32 count_objects;
__u32 pad;
__u32 lessee_id;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 busy;
__u32 handle;
__u32 caching;
__u32 handle;
__u32 tiling_mode;
__u32 stride;
__u32 swizzle_mode;
__u32 handle;
__u32 tiling_mode;
__u32 swizzle_mode;
__u32 phys_swizzle_mode;
__u32 crtc_id;
__u32 pipe;
__u32 handle;
__u32 madv;
__u32 retained;
__u32 flags;
__u32 bo_handle;
__u32 offset_Y; /* offset for packet formats */
__u32 offset_U;
__u32 offset_V;
__u32 crtc_id;
__u32 flags;
__u32 color_key;
__u32 contrast;
__u32 saturation;
__u32 gamma0;
__u32 gamma1;
__u32 gamma2;
__u32 gamma3;
__u32 gamma4;
__u32 gamma5;
__u32 plane_id;
__u32 min_value;
__u32 channel_mask;
__u32 max_value;
__u32 flags;
__u32 bo_handle;
__u32 flags;
__u32 ctx_id;
__u32 pad;
__u32 ctx_id;
__u32 pad;
__u32 ctx_id;
__u32 flags;
__u32 reset_count;
__u32 batch_active;
__u32 batch_pending;
__u32 pad;
__u32 flags;
__u32 handle;
__u32 ctx_id;
__u32 size;
__u32 flags;
__u32 num_properties;
__u32 type;
__u32 n_mux_regs;
__u32 n_boolean_regs;
__u32 n_flex_regs;
__u32 flags;
__u32 num_items;
__u32 flags;
__u32 unused1, unused2, unused3;
__u32 front_bo_handle;
__u32 back_bo_handle;
__u32 unused_bo_handle;
__u32 depth_bo_handle;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 read_domains;
__u32 write_domain;
__u32 handle;
__u32 target_handle;
__u32 delta;
__u32 read_domains;
__u32 write_domain;
__u32 handle;
__u32 relocation_count;
__u32 buffer_count;
__u32 batch_start_offset;
__u32 batch_len;
__u32 DR1;
__u32 DR4;
__u32 num_cliprects;
__u32 handle;
__u32 relocation_count;
__u32 handle;
__u32 flags;
__u32 buffer_count;
__u32 batch_start_offset;
__u32 batch_len;
__u32 DR1;
__u32 DR4;
__u32 num_cliprects;
__u32 request;
__u32 pad;
__u32 handle;
__u32 initial_domain;
__u32 flags;
__u32 flags;
__u32 handle;
__u32 handle;
__u32 tiling_flags;
__u32 pitch;
__u32 handle;
__u32 tiling_flags;
__u32 pitch;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 read_domains;
__u32 write_domain;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 domain;
__u32 handle;
__u32 pad;
__u32 handle;
__u32 pad;
__u32 handle; /* buffer */
__u32 op; /* RADEON_GEM_OP_* */
__u32 handle;
__u32 operation;
__u32 vm_id;
__u32 flags;
__u32 chunk_id;
__u32 length_dw;
__u32 handle;
__u32 read_domains;
__u32 write_domain;
__u32 flags;
__u32 num_chunks;
__u32 cs_id;
typedef __u32 __le32;
typedef __u32 __be32;
static const __u32 crc32_table[256] = {