__SHIFTOUT
val = __SHIFTOUT(val, instr->src.u.reg->mask);
val = __SHIFTOUT(val, instr->dst.u.reg->mask);
__SHIFTOUT(timing, ATA_DEVSLP_EXIT_TIMEOUT);
__SHIFTOUT(timing, ATA_DEVSLP_MIN_ASSERT);
dmfc = __SHIFTOUT(capa, PCI_CORE_CAPID0_A_DMFC);
dmfc = __SHIFTOUT(capb, PCI_CORE_CAPID0_B_DMFC);
size_a = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_A_SIZE);
size_b = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_B_SIZE);
node = __SHIFTOUT(val, PCI_E5_UBOX0_CPUNODEID_LCLNODEID);
ecc_mode0 = __SHIFTOUT(dimm_ch0, MCH_E3_DIMM_ECC);
ecc_mode1 = __SHIFTOUT(dimm_ch1, MCH_E3_DIMM_ECC);
dimm_size[0] = __SHIFTOUT(dimm_ch, dimm_szmask[0]);
dimm_size[1] = __SHIFTOUT(dimm_ch, dimm_szmask[1]);
ecc = __SHIFTOUT(dimm_ch, MCH_E3_DIMM_ECC);
rank = __SHIFTOUT(err0, MCH_E3_ERRLOG0_ERRRANK);
if (__SHIFTOUT(mcmtr, PCI_E5_IMC_CPGC_MCMTR_IMC_MODE) ==
val = __SHIFTOUT(dimmmtr, PCI_E5_IMC_CTAD_DIMMMTR_RANK_CNT);
val = __SHIFTOUT(dimmmtr, PCI_E5_IMC_CTAD_DIMMMTR_DDR3_WIDTH);
val = __SHIFTOUT(dimmmtr, PCI_E5_IMC_CTAD_DIMMMTR_DDR3_DNSTY);
__SHIFTOUT(thr, mask));
ecc_cnt = __SHIFTOUT(err, mask);
dimms = __SHIFTOUT(val, PCI_X3400UC_MC_MAX_DOD_DIMMS);
err0 = __SHIFTOUT(cor, PCI_X3400UC_MCT2_COR_DIMM0);
err1 = __SHIFTOUT(cor, PCI_X3400UC_MCT2_COR_DIMM1);
rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX);
buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN);
buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX);
ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX);
end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX);
ret = __SHIFTOUT(val, ET_MII_STAT_VALUE);
power_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_POWER);
energy_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_ENERGY);
time_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_TIME);
temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_THERM_STATUS_READ);
temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_PKGTM_STATUS_READ);
size_a = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_A_SIZE);
size_b = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_B_SIZE);
temp = __SHIFTOUT(val, dimm_sc->dimm_mask);
temp_lo = __SHIFTOUT(temp_th,
temp_mid = __SHIFTOUT(temp_th,
temp_hi = __SHIFTOUT(temp_th,
temp = __SHIFTOUT(val, PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMP);
gpr = __SHIFTOUT(info, SVM_EXIT_CR_GPR);
exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT);
OS_ASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6);
exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG);
exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR);
seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE);
seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S);
seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL);
seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P);
seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL);
seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L);
seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF);
seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G);
state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v,
if (__SHIFTOUT(descs.eax, CPUID_8_0A_EAX_SvmRev) != 1) {
if (__SHIFTOUT(qual, INTR_INFO_TYPE) != INTR_TYPE_NMI) {
clevel = __SHIFTOUT(cpudata->gprs[NVMM_X64_GPR_RAX],
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
switch (__SHIFTOUT(qual, VMX_QUAL_CR_NUM)) {
exit->u.io.port = __SHIFTOUT(qual, VMX_QUAL_IO_PORT);
OS_ASSERT(__SHIFTOUT(info, VMX_INFO_IO_SEG) < 6);
exit->u.io.seg = __SHIFTOUT(info, VMX_INFO_IO_SEG);
if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_64) {
} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_32) {
} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_16) {
if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_32) {
} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_16) {
} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_8) {
switch (__SHIFTOUT(info, INTR_INFO_TYPE)) {
segs[idx].attrib.type = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_TYPE);
segs[idx].attrib.s = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_S);
segs[idx].attrib.dpl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DPL);
segs[idx].attrib.p = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_P);
segs[idx].attrib.avl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_AVL);
segs[idx].attrib.l = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_L);
segs[idx].attrib.def = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DEF);
segs[idx].attrib.g = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_G);
if (__SHIFTOUT(msr, IA32_VMX_BASIC_MEM_TYPE) != MEM_TYPE_WB) {
#define __SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask))
if (__SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID) == 120) {
if (__SHIFTOUT(val, LAPIC_ID_MASK) == 120) {