__SHIFTIN
val = __SHIFTIN(val, instr->dst.u.reg->mask);
val = __SHIFTIN(val, instr->src.u.reg->mask);
val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
__SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
__SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
val = __SHIFTIN(56, ET_IPG_NONB2B_1) |
__SHIFTIN(88, ET_IPG_NONB2B_2) |
__SHIFTIN(80, ET_IPG_MINIFG) |
__SHIFTIN(96, ET_IPG_B2B);
val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
__SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
__SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
val = __SHIFTIN(ET_RXMAC_SEGSZ(256), ET_RXMAC_MC_SEGSZ_MAX) |
val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG;
val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize,
val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize,
rxstat_pos = __SHIFTIN(rxst_ring->rsr_index,
rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX);
td->td_ctrl1 = __SHIFTIN(segs[i].ds_len, ET_TDCTRL1_LEN);
tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index,
__SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN);
desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX);
val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
__SHIFTIN(reg, ET_MII_ADDR_REG);
val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
__SHIFTIN(reg, ET_MII_ADDR_REG);
CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE));
#define ET_PCIV_L0S_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L0S_LATENCY)
#define ET_PCIV_L1_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L1_LATENCY)
__SHIFTIN(ncpus - 1, CPUID_8_08_ECX_NC) |
__SHIFTIN(ilog2(NVMM_MAX_VCPUS), CPUID_8_08_ECX_ApicIdSize);
__SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) |
__SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) |
__SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) |
__SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) |
__SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) |
__SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) |
__SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) |
__SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G);
vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8],
__SHIFTIN((uint64_t)vector, VMCB_CTRL_EVENTINJ_VECTOR) |
__SHIFTIN((uint64_t)type, VMCB_CTRL_EVENTINJ_TYPE) |
__SHIFTIN((uint64_t)err, VMCB_CTRL_EVENTINJ_EV) |
__SHIFTIN((uint64_t)1, VMCB_CTRL_EVENTINJ_V) |
__SHIFTIN((uint64_t)error, VMCB_CTRL_EVENTINJ_ERRORCODE);
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(ncpus,
__SHIFTIN((uint64_t)vector, INTR_INFO_VECTOR) |
__SHIFTIN((uint64_t)type, INTR_INFO_TYPE) |
__SHIFTIN((uint64_t)err, INTR_INFO_ERROR) |
__SHIFTIN((uint64_t)1, INTR_INFO_VALID);
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(ncpus,
__SHIFTIN(ncpus - 1, CPUID_0_04_EAX_SHARING);
__SHIFTIN(0, CPUID_0_04_EAX_SHARING);
__SHIFTIN(ncpus - 1, CPUID_0_04_EAX_CORE_P_PKG);
__SHIFTIN(ecx, CPUID_0_0B_ECX_LVLNUM) |
__SHIFTIN(CPUID_0_0B_ECX_LVLTYPE_SMT, CPUID_0_0B_ECX_LVLTYPE);
__SHIFTIN(ecx, CPUID_0_0B_ECX_LVLNUM) |
__SHIFTIN(CPUID_0_0B_ECX_LVLTYPE_CORE, CPUID_0_0B_ECX_LVLTYPE);
__SHIFTIN(segs[idx].attrib.type, VMX_SEG_ATTRIB_TYPE) |
__SHIFTIN(segs[idx].attrib.s, VMX_SEG_ATTRIB_S) |
__SHIFTIN(segs[idx].attrib.dpl, VMX_SEG_ATTRIB_DPL) |
__SHIFTIN(segs[idx].attrib.p, VMX_SEG_ATTRIB_P) |
__SHIFTIN(segs[idx].attrib.avl, VMX_SEG_ATTRIB_AVL) |
__SHIFTIN(segs[idx].attrib.l, VMX_SEG_ATTRIB_L) |
__SHIFTIN(segs[idx].attrib.def, VMX_SEG_ATTRIB_DEF) |
__SHIFTIN(segs[idx].attrib.g, VMX_SEG_ATTRIB_G) |
vmcs->ident = __SHIFTIN(rev, VMCS_IDENT_REVISION);
__SHIFTIN(vmx_eptp_type, EPTP_TYPE) |
__SHIFTIN(4-1, EPTP_WALKLEN) |
vmxon->ident = __SHIFTIN(revision, VMXON_IDENT_REVISION);