sys/dev/drm/amd/display/dc/bios/command_table.c

123

BIOS_CMD_TABLE_PARA_REVISION(DIGxEncoderControl);

sys/dev/drm/amd/display/dc/bios/command_table.c

1239

switch (BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1254

BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL));

sys/dev/drm/amd/display/dc/bios/command_table.c

1442

switch (BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1451

BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll));

sys/dev/drm/amd/display/dc/bios/command_table.c

1553

switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1EncoderControl)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1561

switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2EncoderControl)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

157

if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG1EncoderControl))

sys/dev/drm/amd/display/dc/bios/command_table.c

162

if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG2EncoderControl))

sys/dev/drm/amd/display/dc/bios/command_table.c

1647

switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1OutputControl)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1655

switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2OutputControl)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1717

BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_UsingDTDTiming);

sys/dev/drm/amd/display/dc/bios/command_table.c

1731

switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_Timing)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1737

BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_Timing));

sys/dev/drm/amd/display/dc/bios/command_table.c

1916

switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1925

BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source));

sys/dev/drm/amd/display/dc/bios/command_table.c

2028

switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTC)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

2034

BIOS_CMD_TABLE_PARA_REVISION(EnableCRTC));

sys/dev/drm/amd/display/dc/bios/command_table.c

2080

switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTCMemReq)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

2133

switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

2142

BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock));

sys/dev/drm/amd/display/dc/bios/command_table.c

2233

switch (BIOS_CMD_TABLE_PARA_REVISION(ExternalEncoderControl)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

2361

switch (BIOS_CMD_TABLE_PARA_REVISION(EnableDispPowerGating)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

2368

BIOS_CMD_TABLE_PARA_REVISION(EnableDispPowerGating));

sys/dev/drm/amd/display/dc/bios/command_table.c

2411

switch (BIOS_CMD_TABLE_PARA_REVISION(SetDCEClock)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

2417

BIOS_CMD_TABLE_PARA_REVISION(SetDCEClock));

sys/dev/drm/amd/display/dc/bios/command_table.c

920

switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

935

BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock));

sys/dev/drm/amd/display/dc/bios/command_table2.c

246

switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {

sys/dev/drm/amd/display/dc/bios/command_table2.c

252

BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));

sys/dev/drm/amd/display/dc/bios/command_table2.c

355

BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);

sys/dev/drm/amd/display/dc/bios/command_table2.c

478

switch (BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)) {

sys/dev/drm/amd/display/dc/bios/command_table2.c

484

BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source));

sys/dev/drm/amd/display/dc/bios/command_table2.c

547

switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) {

sys/dev/drm/amd/display/dc/bios/command_table2.c

553

BIOS_CMD_TABLE_PARA_REVISION(enablecrtc));

sys/dev/drm/amd/display/dc/bios/command_table2.c

609

switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) {

sys/dev/drm/amd/display/dc/bios/command_table2.c

644

switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) {

sys/dev/drm/amd/display/dc/bios/command_table2.c

651

BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating));

sys/dev/drm/amd/display/dc/bios/command_table2.c

696

switch (BIOS_CMD_TABLE_PARA_REVISION(setdceclock)) {

sys/dev/drm/amd/display/dc/bios/command_table2.c

702

BIOS_CMD_TABLE_PARA_REVISION(setdceclock));

sys/dev/drm/amd/display/dc/bios/command_table2.c

93

BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol);