sys/dev/drm/i915/i915_oa_cflgt3.c

35

{ _MMIO(0x2740), 0x00000000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

36

{ _MMIO(0x2744), 0x00800000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

37

{ _MMIO(0x2714), 0xf0800000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

38

{ _MMIO(0x2710), 0x00000000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

39

{ _MMIO(0x2724), 0xf0800000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

40

{ _MMIO(0x2720), 0x00000000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

41

{ _MMIO(0x2770), 0x00000004 },

sys/dev/drm/i915/i915_oa_cflgt3.c

42

{ _MMIO(0x2774), 0x00000000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

43

{ _MMIO(0x2778), 0x00000003 },

sys/dev/drm/i915/i915_oa_cflgt3.c

44

{ _MMIO(0x277c), 0x00000000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

45

{ _MMIO(0x2780), 0x00000007 },

sys/dev/drm/i915/i915_oa_cflgt3.c

46

{ _MMIO(0x2784), 0x00000000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

47

{ _MMIO(0x2788), 0x00100002 },

sys/dev/drm/i915/i915_oa_cflgt3.c

48

{ _MMIO(0x278c), 0x0000fff7 },

sys/dev/drm/i915/i915_oa_cflgt3.c

49

{ _MMIO(0x2790), 0x00100002 },

sys/dev/drm/i915/i915_oa_cflgt3.c

50

{ _MMIO(0x2794), 0x0000ffcf },

sys/dev/drm/i915/i915_oa_cflgt3.c

51

{ _MMIO(0x2798), 0x00100082 },

sys/dev/drm/i915/i915_oa_cflgt3.c

52

{ _MMIO(0x279c), 0x0000ffef },

sys/dev/drm/i915/i915_oa_cflgt3.c

53

{ _MMIO(0x27a0), 0x001000c2 },

sys/dev/drm/i915/i915_oa_cflgt3.c

54

{ _MMIO(0x27a4), 0x0000ffe7 },

sys/dev/drm/i915/i915_oa_cflgt3.c

55

{ _MMIO(0x27a8), 0x00100001 },

sys/dev/drm/i915/i915_oa_cflgt3.c

56

{ _MMIO(0x27ac), 0x0000ffe7 },

sys/dev/drm/i915/i915_oa_cflgt3.c

63

{ _MMIO(0x9840), 0x00000080 },

sys/dev/drm/i915/i915_oa_cflgt3.c

64

{ _MMIO(0x9888), 0x11810000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

65

{ _MMIO(0x9888), 0x07810013 },

sys/dev/drm/i915/i915_oa_cflgt3.c

66

{ _MMIO(0x9888), 0x1f810000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

67

{ _MMIO(0x9888), 0x1d810000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

68

{ _MMIO(0x9888), 0x1b930040 },

sys/dev/drm/i915/i915_oa_cflgt3.c

69

{ _MMIO(0x9888), 0x07e54000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

70

{ _MMIO(0x9888), 0x1f908000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

71

{ _MMIO(0x9888), 0x11900000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

72

{ _MMIO(0x9888), 0x37900000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

73

{ _MMIO(0x9888), 0x53900000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

74

{ _MMIO(0x9888), 0x45900000 },

sys/dev/drm/i915/i915_oa_cflgt3.c

75

{ _MMIO(0x9888), 0x33900000 },

sys/dev/drm/i915/i915_oa_cnl.c

35

{ _MMIO(0x2740), 0x00000000 },

sys/dev/drm/i915/i915_oa_cnl.c

36

{ _MMIO(0x2710), 0x00000000 },

sys/dev/drm/i915/i915_oa_cnl.c

37

{ _MMIO(0x2714), 0xf0800000 },

sys/dev/drm/i915/i915_oa_cnl.c

38

{ _MMIO(0x2720), 0x00000000 },

sys/dev/drm/i915/i915_oa_cnl.c

39

{ _MMIO(0x2724), 0xf0800000 },

sys/dev/drm/i915/i915_oa_cnl.c

40

{ _MMIO(0x2770), 0x00000004 },

sys/dev/drm/i915/i915_oa_cnl.c

41

{ _MMIO(0x2774), 0x0000ffff },

sys/dev/drm/i915/i915_oa_cnl.c

42

{ _MMIO(0x2778), 0x00000003 },

sys/dev/drm/i915/i915_oa_cnl.c

43

{ _MMIO(0x277c), 0x0000ffff },

sys/dev/drm/i915/i915_oa_cnl.c

44

{ _MMIO(0x2780), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

45

{ _MMIO(0x2784), 0x0000ffff },

sys/dev/drm/i915/i915_oa_cnl.c

46

{ _MMIO(0x2788), 0x00100002 },

sys/dev/drm/i915/i915_oa_cnl.c

47

{ _MMIO(0x278c), 0x0000fff7 },

sys/dev/drm/i915/i915_oa_cnl.c

48

{ _MMIO(0x2790), 0x00100002 },

sys/dev/drm/i915/i915_oa_cnl.c

49

{ _MMIO(0x2794), 0x0000ffcf },

sys/dev/drm/i915/i915_oa_cnl.c

50

{ _MMIO(0x2798), 0x00100082 },

sys/dev/drm/i915/i915_oa_cnl.c

51

{ _MMIO(0x279c), 0x0000ffef },

sys/dev/drm/i915/i915_oa_cnl.c

52

{ _MMIO(0x27a0), 0x001000c2 },

sys/dev/drm/i915/i915_oa_cnl.c

53

{ _MMIO(0x27a4), 0x0000ffe7 },

sys/dev/drm/i915/i915_oa_cnl.c

54

{ _MMIO(0x27a8), 0x00100001 },

sys/dev/drm/i915/i915_oa_cnl.c

55

{ _MMIO(0x27ac), 0x0000ffe7 },

sys/dev/drm/i915/i915_oa_cnl.c

62

{ _MMIO(0xd04), 0x00000200 },

sys/dev/drm/i915/i915_oa_cnl.c

63

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

64

{ _MMIO(0x9888), 0x17060000 },

sys/dev/drm/i915/i915_oa_cnl.c

65

{ _MMIO(0x9840), 0x00000000 },

sys/dev/drm/i915/i915_oa_cnl.c

66

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

67

{ _MMIO(0x9888), 0x13034000 },

sys/dev/drm/i915/i915_oa_cnl.c

68

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

69

{ _MMIO(0x9888), 0x07060066 },

sys/dev/drm/i915/i915_oa_cnl.c

70

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

71

{ _MMIO(0x9888), 0x05060000 },

sys/dev/drm/i915/i915_oa_cnl.c

72

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

73

{ _MMIO(0x9888), 0x0f080040 },

sys/dev/drm/i915/i915_oa_cnl.c

74

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

75

{ _MMIO(0x9888), 0x07091000 },

sys/dev/drm/i915/i915_oa_cnl.c

76

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

77

{ _MMIO(0x9888), 0x0f041000 },

sys/dev/drm/i915/i915_oa_cnl.c

78

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

79

{ _MMIO(0x9888), 0x1d004000 },

sys/dev/drm/i915/i915_oa_cnl.c

80

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

81

{ _MMIO(0x9888), 0x35000000 },

sys/dev/drm/i915/i915_oa_cnl.c

82

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

83

{ _MMIO(0x9888), 0x49000000 },

sys/dev/drm/i915/i915_oa_cnl.c

84

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

85

{ _MMIO(0x9888), 0x3d000000 },

sys/dev/drm/i915/i915_oa_cnl.c

86

{ _MMIO(0x9884), 0x00000007 },

sys/dev/drm/i915/i915_oa_cnl.c

87

{ _MMIO(0x9888), 0x31000000 },

sys/dev/drm/i915/i915_oa_hsw.c

100

{ _MMIO(0x26410), 0x000000a0 },

sys/dev/drm/i915/i915_oa_hsw.c

101

{ _MMIO(0x26404), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

102

{ _MMIO(0x25420), 0x04108020 },

sys/dev/drm/i915/i915_oa_hsw.c

103

{ _MMIO(0x25424), 0x1284a420 },

sys/dev/drm/i915/i915_oa_hsw.c

104

{ _MMIO(0x2541c), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

105

{ _MMIO(0x25428), 0x00042049 },

sys/dev/drm/i915/i915_oa_hsw.c

36

{ _MMIO(0x2724), 0x00800000 },

sys/dev/drm/i915/i915_oa_hsw.c

37

{ _MMIO(0x2720), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

38

{ _MMIO(0x2714), 0x00800000 },

sys/dev/drm/i915/i915_oa_hsw.c

39

{ _MMIO(0x2710), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

46

{ _MMIO(0x9840), 0x00000080 },

sys/dev/drm/i915/i915_oa_hsw.c

47

{ _MMIO(0x253a4), 0x01600000 },

sys/dev/drm/i915/i915_oa_hsw.c

48

{ _MMIO(0x25440), 0x00100000 },

sys/dev/drm/i915/i915_oa_hsw.c

49

{ _MMIO(0x25128), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

50

{ _MMIO(0x2691c), 0x00000800 },

sys/dev/drm/i915/i915_oa_hsw.c

51

{ _MMIO(0x26aa0), 0x01500000 },

sys/dev/drm/i915/i915_oa_hsw.c

52

{ _MMIO(0x26b9c), 0x00006000 },

sys/dev/drm/i915/i915_oa_hsw.c

53

{ _MMIO(0x2791c), 0x00000800 },

sys/dev/drm/i915/i915_oa_hsw.c

54

{ _MMIO(0x27aa0), 0x01500000 },

sys/dev/drm/i915/i915_oa_hsw.c

55

{ _MMIO(0x27b9c), 0x00006000 },

sys/dev/drm/i915/i915_oa_hsw.c

56

{ _MMIO(0x2641c), 0x00000400 },

sys/dev/drm/i915/i915_oa_hsw.c

57

{ _MMIO(0x25380), 0x00000010 },

sys/dev/drm/i915/i915_oa_hsw.c

58

{ _MMIO(0x2538c), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

59

{ _MMIO(0x25384), 0x0800aaaa },

sys/dev/drm/i915/i915_oa_hsw.c

60

{ _MMIO(0x25400), 0x00000004 },

sys/dev/drm/i915/i915_oa_hsw.c

61

{ _MMIO(0x2540c), 0x06029000 },

sys/dev/drm/i915/i915_oa_hsw.c

62

{ _MMIO(0x25410), 0x00000002 },

sys/dev/drm/i915/i915_oa_hsw.c

63

{ _MMIO(0x25404), 0x5c30ffff },

sys/dev/drm/i915/i915_oa_hsw.c

64

{ _MMIO(0x25100), 0x00000016 },

sys/dev/drm/i915/i915_oa_hsw.c

65

{ _MMIO(0x25110), 0x00000400 },

sys/dev/drm/i915/i915_oa_hsw.c

66

{ _MMIO(0x25104), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

67

{ _MMIO(0x26804), 0x00001211 },

sys/dev/drm/i915/i915_oa_hsw.c

68

{ _MMIO(0x26884), 0x00000100 },

sys/dev/drm/i915/i915_oa_hsw.c

69

{ _MMIO(0x26900), 0x00000002 },

sys/dev/drm/i915/i915_oa_hsw.c

70

{ _MMIO(0x26908), 0x00700000 },

sys/dev/drm/i915/i915_oa_hsw.c

71

{ _MMIO(0x26904), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

72

{ _MMIO(0x26984), 0x00001022 },

sys/dev/drm/i915/i915_oa_hsw.c

73

{ _MMIO(0x26a04), 0x00000011 },

sys/dev/drm/i915/i915_oa_hsw.c

74

{ _MMIO(0x26a80), 0x00000006 },

sys/dev/drm/i915/i915_oa_hsw.c

75

{ _MMIO(0x26a88), 0x00000c02 },

sys/dev/drm/i915/i915_oa_hsw.c

76

{ _MMIO(0x26a84), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

77

{ _MMIO(0x26b04), 0x00001000 },

sys/dev/drm/i915/i915_oa_hsw.c

78

{ _MMIO(0x26b80), 0x00000002 },

sys/dev/drm/i915/i915_oa_hsw.c

79

{ _MMIO(0x26b8c), 0x00000007 },

sys/dev/drm/i915/i915_oa_hsw.c

80

{ _MMIO(0x26b84), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

81

{ _MMIO(0x27804), 0x00004844 },

sys/dev/drm/i915/i915_oa_hsw.c

82

{ _MMIO(0x27884), 0x00000400 },

sys/dev/drm/i915/i915_oa_hsw.c

83

{ _MMIO(0x27900), 0x00000002 },

sys/dev/drm/i915/i915_oa_hsw.c

84

{ _MMIO(0x27908), 0x0e000000 },

sys/dev/drm/i915/i915_oa_hsw.c

85

{ _MMIO(0x27904), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

86

{ _MMIO(0x27984), 0x00004088 },

sys/dev/drm/i915/i915_oa_hsw.c

87

{ _MMIO(0x27a04), 0x00000044 },

sys/dev/drm/i915/i915_oa_hsw.c

88

{ _MMIO(0x27a80), 0x00000006 },

sys/dev/drm/i915/i915_oa_hsw.c

89

{ _MMIO(0x27a88), 0x00018040 },

sys/dev/drm/i915/i915_oa_hsw.c

90

{ _MMIO(0x27a84), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

91

{ _MMIO(0x27b04), 0x00004000 },

sys/dev/drm/i915/i915_oa_hsw.c

92

{ _MMIO(0x27b80), 0x00000002 },

sys/dev/drm/i915/i915_oa_hsw.c

93

{ _MMIO(0x27b8c), 0x000000e0 },

sys/dev/drm/i915/i915_oa_hsw.c

94

{ _MMIO(0x27b84), 0x00000000 },

sys/dev/drm/i915/i915_oa_hsw.c

95

{ _MMIO(0x26104), 0x00002222 },

sys/dev/drm/i915/i915_oa_hsw.c

96

{ _MMIO(0x26184), 0x0c006666 },

sys/dev/drm/i915/i915_oa_hsw.c

97

{ _MMIO(0x26284), 0x04000000 },

sys/dev/drm/i915/i915_oa_hsw.c

98

{ _MMIO(0x26304), 0x04000000 },

sys/dev/drm/i915/i915_oa_hsw.c

99

{ _MMIO(0x26400), 0x00000002 },

sys/dev/drm/i915/i915_oa_icl.c

35

{ _MMIO(0x2740), 0x00000000 },

sys/dev/drm/i915/i915_oa_icl.c

36

{ _MMIO(0x2710), 0x00000000 },

sys/dev/drm/i915/i915_oa_icl.c

37

{ _MMIO(0x2714), 0xf0800000 },

sys/dev/drm/i915/i915_oa_icl.c

38

{ _MMIO(0x2720), 0x00000000 },

sys/dev/drm/i915/i915_oa_icl.c

39

{ _MMIO(0x2724), 0xf0800000 },

sys/dev/drm/i915/i915_oa_icl.c

40

{ _MMIO(0x2770), 0x00000004 },

sys/dev/drm/i915/i915_oa_icl.c

41

{ _MMIO(0x2774), 0x0000ffff },

sys/dev/drm/i915/i915_oa_icl.c

42

{ _MMIO(0x2778), 0x00000003 },

sys/dev/drm/i915/i915_oa_icl.c

43

{ _MMIO(0x277c), 0x0000ffff },

sys/dev/drm/i915/i915_oa_icl.c

44

{ _MMIO(0x2780), 0x00000007 },

sys/dev/drm/i915/i915_oa_icl.c

45

{ _MMIO(0x2784), 0x0000ffff },

sys/dev/drm/i915/i915_oa_icl.c

46

{ _MMIO(0x2788), 0x00100002 },

sys/dev/drm/i915/i915_oa_icl.c

47

{ _MMIO(0x278c), 0x0000fff7 },

sys/dev/drm/i915/i915_oa_icl.c

48

{ _MMIO(0x2790), 0x00100002 },

sys/dev/drm/i915/i915_oa_icl.c

49

{ _MMIO(0x2794), 0x0000ffcf },

sys/dev/drm/i915/i915_oa_icl.c

50

{ _MMIO(0x2798), 0x00100082 },

sys/dev/drm/i915/i915_oa_icl.c

51

{ _MMIO(0x279c), 0x0000ffef },

sys/dev/drm/i915/i915_oa_icl.c

52

{ _MMIO(0x27a0), 0x001000c2 },

sys/dev/drm/i915/i915_oa_icl.c

53

{ _MMIO(0x27a4), 0x0000ffe7 },

sys/dev/drm/i915/i915_oa_icl.c

54

{ _MMIO(0x27a8), 0x00100001 },

sys/dev/drm/i915/i915_oa_icl.c

55

{ _MMIO(0x27ac), 0x0000ffe7 },

sys/dev/drm/i915/i915_oa_icl.c

62

{ _MMIO(0xd04), 0x00000200 },

sys/dev/drm/i915/i915_oa_icl.c

63

{ _MMIO(0x9840), 0x00000000 },

sys/dev/drm/i915/i915_oa_icl.c

64

{ _MMIO(0x9884), 0x00000000 },

sys/dev/drm/i915/i915_oa_icl.c

65

{ _MMIO(0x9888), 0x10060000 },

sys/dev/drm/i915/i915_oa_icl.c

66

{ _MMIO(0x9888), 0x22060000 },

sys/dev/drm/i915/i915_oa_icl.c

67

{ _MMIO(0x9888), 0x16060000 },

sys/dev/drm/i915/i915_oa_icl.c

68

{ _MMIO(0x9888), 0x24060000 },

sys/dev/drm/i915/i915_oa_icl.c

69

{ _MMIO(0x9888), 0x18060000 },

sys/dev/drm/i915/i915_oa_icl.c

70

{ _MMIO(0x9888), 0x1a060000 },

sys/dev/drm/i915/i915_oa_icl.c

71

{ _MMIO(0x9888), 0x12060000 },

sys/dev/drm/i915/i915_oa_icl.c

72

{ _MMIO(0x9888), 0x14060000 },

sys/dev/drm/i915/i915_oa_icl.c

73

{ _MMIO(0x9888), 0x10060000 },

sys/dev/drm/i915/i915_oa_icl.c

74

{ _MMIO(0x9888), 0x22060000 },

sys/dev/drm/i915/i915_oa_icl.c

75

{ _MMIO(0x9884), 0x00000003 },

sys/dev/drm/i915/i915_oa_icl.c

76

{ _MMIO(0x9888), 0x16130000 },

sys/dev/drm/i915/i915_oa_icl.c

77

{ _MMIO(0x9888), 0x24000001 },

sys/dev/drm/i915/i915_oa_icl.c

78

{ _MMIO(0x9888), 0x0e130056 },

sys/dev/drm/i915/i915_oa_icl.c

79

{ _MMIO(0x9888), 0x10130000 },

sys/dev/drm/i915/i915_oa_icl.c

80

{ _MMIO(0x9888), 0x1a130000 },

sys/dev/drm/i915/i915_oa_icl.c

81

{ _MMIO(0x9888), 0x541f0001 },

sys/dev/drm/i915/i915_oa_icl.c

82

{ _MMIO(0x9888), 0x181f0000 },

sys/dev/drm/i915/i915_oa_icl.c

83

{ _MMIO(0x9888), 0x4c1f0000 },

sys/dev/drm/i915/i915_oa_icl.c

84

{ _MMIO(0x9888), 0x301f0000 },

sys/dev/drm/i915/i915_perf.c

3096

oa_regs[i].addr = _MMIO(addr);

sys/dev/drm/i915/i915_pvinfo.h

114

_MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))

sys/dev/drm/i915/i915_reg.h

1000

#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)

sys/dev/drm/i915/i915_reg.h

1001

#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)

sys/dev/drm/i915/i915_reg.h

10400

#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */

sys/dev/drm/i915/i915_reg.h

10412

#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */

sys/dev/drm/i915/i915_reg.h

10414

#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */

sys/dev/drm/i915/i915_reg.h

10415

#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */

sys/dev/drm/i915/i915_reg.h

10416

#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */

sys/dev/drm/i915/i915_reg.h

10417

#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */

sys/dev/drm/i915/i915_reg.h

10418

#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */

sys/dev/drm/i915/i915_reg.h

10420

#define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

10422

#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)

sys/dev/drm/i915/i915_reg.h

10428

#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)

sys/dev/drm/i915/i915_reg.h

10434

#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */

sys/dev/drm/i915/i915_reg.h

10445

#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)

sys/dev/drm/i915/i915_reg.h

10446

#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)

sys/dev/drm/i915/i915_reg.h

10466

#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)

sys/dev/drm/i915/i915_reg.h

10467

#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)

sys/dev/drm/i915/i915_reg.h

10480

#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)

sys/dev/drm/i915/i915_reg.h

10481

#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)

sys/dev/drm/i915/i915_reg.h

10495

#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)

sys/dev/drm/i915/i915_reg.h

10496

#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)

sys/dev/drm/i915/i915_reg.h

10510

#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)

sys/dev/drm/i915/i915_reg.h

10511

#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)

sys/dev/drm/i915/i915_reg.h

10525

#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)

sys/dev/drm/i915/i915_reg.h

10526

#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)

sys/dev/drm/i915/i915_reg.h

10540

#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)

sys/dev/drm/i915/i915_reg.h

10541

#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)

sys/dev/drm/i915/i915_reg.h

10557

#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)

sys/dev/drm/i915/i915_reg.h

10558

#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)

sys/dev/drm/i915/i915_reg.h

10572

#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)

sys/dev/drm/i915/i915_reg.h

10573

#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)

sys/dev/drm/i915/i915_reg.h

10587

#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)

sys/dev/drm/i915/i915_reg.h

10588

#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)

sys/dev/drm/i915/i915_reg.h

10602

#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)

sys/dev/drm/i915/i915_reg.h

10603

#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)

sys/dev/drm/i915/i915_reg.h

10619

#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)

sys/dev/drm/i915/i915_reg.h

10620

#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)

sys/dev/drm/i915/i915_reg.h

10632

#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)

sys/dev/drm/i915/i915_reg.h

10633

#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)

sys/dev/drm/i915/i915_reg.h

10645

#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)

sys/dev/drm/i915/i915_reg.h

10646

#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)

sys/dev/drm/i915/i915_reg.h

10658

#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)

sys/dev/drm/i915/i915_reg.h

10659

#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)

sys/dev/drm/i915/i915_reg.h

10671

#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)

sys/dev/drm/i915/i915_reg.h

10672

#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)

sys/dev/drm/i915/i915_reg.h

10684

#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)

sys/dev/drm/i915/i915_reg.h

10685

#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)

sys/dev/drm/i915/i915_reg.h

10700

#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)

sys/dev/drm/i915/i915_reg.h

10701

#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)

sys/dev/drm/i915/i915_reg.h

10702

#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)

sys/dev/drm/i915/i915_reg.h

10703

#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)

sys/dev/drm/i915/i915_reg.h

10725

#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)

sys/dev/drm/i915/i915_reg.h

10726

#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)

sys/dev/drm/i915/i915_reg.h

10727

#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)

sys/dev/drm/i915/i915_reg.h

10728

#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)

sys/dev/drm/i915/i915_reg.h

10750

#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)

sys/dev/drm/i915/i915_reg.h

10757

#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)

sys/dev/drm/i915/i915_reg.h

10760

#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)

sys/dev/drm/i915/i915_reg.h

1170

#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)

sys/dev/drm/i915/i915_reg.h

125

#define INVALID_MMIO_REG _MMIO(0)

sys/dev/drm/i915/i915_reg.h

1531

_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))

sys/dev/drm/i915/i915_reg.h

1537

_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))

sys/dev/drm/i915/i915_reg.h

1539

#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)

sys/dev/drm/i915/i915_reg.h

161

#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))

sys/dev/drm/i915/i915_reg.h

1624

#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \

sys/dev/drm/i915/i915_reg.h

1634

#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)

sys/dev/drm/i915/i915_reg.h

165

#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))

sys/dev/drm/i915/i915_reg.h

167

#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))

sys/dev/drm/i915/i915_reg.h

168

#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))

sys/dev/drm/i915/i915_reg.h

169

#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))

sys/dev/drm/i915/i915_reg.h

1704

#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \

sys/dev/drm/i915/i915_reg.h

171

#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))

sys/dev/drm/i915/i915_reg.h

1712

#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \

sys/dev/drm/i915/i915_reg.h

173

#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))

sys/dev/drm/i915/i915_reg.h

1765

#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))

sys/dev/drm/i915/i915_reg.h

1766

#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))

sys/dev/drm/i915/i915_reg.h

1793

#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))

sys/dev/drm/i915/i915_reg.h

1794

#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))

sys/dev/drm/i915/i915_reg.h

1795

#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \

sys/dev/drm/i915/i915_reg.h

1808

#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \

sys/dev/drm/i915/i915_reg.h

1824

#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))

sys/dev/drm/i915/i915_reg.h

1825

#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))

sys/dev/drm/i915/i915_reg.h

1849

#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))

sys/dev/drm/i915/i915_reg.h

1850

#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))

sys/dev/drm/i915/i915_reg.h

1855

_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

sys/dev/drm/i915/i915_reg.h

2039

_MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))

sys/dev/drm/i915/i915_reg.h

2057

#define CNL_PORT_COMP_DW0 _MMIO(0x162100)

sys/dev/drm/i915/i915_reg.h

2059

#define CNL_PORT_COMP_DW1 _MMIO(0x162104)

sys/dev/drm/i915/i915_reg.h

2060

#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)

sys/dev/drm/i915/i915_reg.h

2071

#define CNL_PORT_COMP_DW9 _MMIO(0x162124)

sys/dev/drm/i915/i915_reg.h

2072

#define CNL_PORT_COMP_DW10 _MMIO(0x162128)

sys/dev/drm/i915/i915_reg.h

2097

#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)

sys/dev/drm/i915/i915_reg.h

2238

_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \

sys/dev/drm/i915/i915_reg.h

2243

#define UAIMI_SPR1 _MMIO(0x4F074)

sys/dev/drm/i915/i915_reg.h

2247

#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)

sys/dev/drm/i915/i915_reg.h

2265

#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)

sys/dev/drm/i915/i915_reg.h

2278

#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)

sys/dev/drm/i915/i915_reg.h

2279

#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)

sys/dev/drm/i915/i915_reg.h

2285

#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)

sys/dev/drm/i915/i915_reg.h

2286

#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)

sys/dev/drm/i915/i915_reg.h

2292

#define TILECTL _MMIO(0x101000)

sys/dev/drm/i915/i915_reg.h

2301

#define PGTBL_CTL _MMIO(0x02020)

sys/dev/drm/i915/i915_reg.h

2304

#define PGTBL_ER _MMIO(0x02024)

sys/dev/drm/i915/i915_reg.h

2324

#define RING_TAIL(base) _MMIO((base) + 0x30)

sys/dev/drm/i915/i915_reg.h

2325

#define RING_HEAD(base) _MMIO((base) + 0x34)

sys/dev/drm/i915/i915_reg.h

2326

#define RING_START(base) _MMIO((base) + 0x38)

sys/dev/drm/i915/i915_reg.h

2327

#define RING_CTL(base) _MMIO((base) + 0x3c)

sys/dev/drm/i915/i915_reg.h

2329

#define RING_SYNC_0(base) _MMIO((base) + 0x40)

sys/dev/drm/i915/i915_reg.h

2330

#define RING_SYNC_1(base) _MMIO((base) + 0x44)

sys/dev/drm/i915/i915_reg.h

2331

#define RING_SYNC_2(base) _MMIO((base) + 0x48)

sys/dev/drm/i915/i915_reg.h

2345

#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)

sys/dev/drm/i915/i915_reg.h

2346

#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)

sys/dev/drm/i915/i915_reg.h

2347

#define RING_HWS_PGA(base) _MMIO((base) + 0x80)

sys/dev/drm/i915/i915_reg.h

2348

#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)

sys/dev/drm/i915/i915_reg.h

2349

#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)

sys/dev/drm/i915/i915_reg.h

2352

#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)

sys/dev/drm/i915/i915_reg.h

2354

#define HSW_GTT_CACHE_EN _MMIO(0x4024)

sys/dev/drm/i915/i915_reg.h

2356

#define GEN7_WR_WATERMARK _MMIO(0x4028)

sys/dev/drm/i915/i915_reg.h

2357

#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)

sys/dev/drm/i915/i915_reg.h

2358

#define ARB_MODE _MMIO(0x4030)

sys/dev/drm/i915/i915_reg.h

2361

#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)

sys/dev/drm/i915/i915_reg.h

2362

#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)

sys/dev/drm/i915/i915_reg.h

2364

#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)

sys/dev/drm/i915/i915_reg.h

2366

#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)

sys/dev/drm/i915/i915_reg.h

2367

#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)

sys/dev/drm/i915/i915_reg.h

2369

#define GAMTARBMODE _MMIO(0x04a08)

sys/dev/drm/i915/i915_reg.h

2372

#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)

sys/dev/drm/i915/i915_reg.h

2373

#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)

sys/dev/drm/i915/i915_reg.h

2374

#define GEN8_RING_FAULT_REG _MMIO(0x4094)

sys/dev/drm/i915/i915_reg.h

2380

#define DONE_REG _MMIO(0x40b0)

sys/dev/drm/i915/i915_reg.h

2381

#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)

sys/dev/drm/i915/i915_reg.h

2382

#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)

sys/dev/drm/i915/i915_reg.h

2383

#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)

sys/dev/drm/i915/i915_reg.h

2384

#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)

sys/dev/drm/i915/i915_reg.h

2385

#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)

sys/dev/drm/i915/i915_reg.h

2386

#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)

sys/dev/drm/i915/i915_reg.h

2387

#define RING_ACTHD(base) _MMIO((base) + 0x74)

sys/dev/drm/i915/i915_reg.h

2388

#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)

sys/dev/drm/i915/i915_reg.h

2389

#define RING_NOPID(base) _MMIO((base) + 0x94)

sys/dev/drm/i915/i915_reg.h

2390

#define RING_IMR(base) _MMIO((base) + 0xa8)

sys/dev/drm/i915/i915_reg.h

2391

#define RING_HWSTAM(base) _MMIO((base) + 0x98)

sys/dev/drm/i915/i915_reg.h

2392

#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)

sys/dev/drm/i915/i915_reg.h

2393

#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)

sys/dev/drm/i915/i915_reg.h

2410

#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)

sys/dev/drm/i915/i915_reg.h

2413

#define GEN7_TLB_RD_ADDR _MMIO(0x4700)

sys/dev/drm/i915/i915_reg.h

2415

#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)

sys/dev/drm/i915/i915_reg.h

2418

#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)

sys/dev/drm/i915/i915_reg.h

2421

#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)

sys/dev/drm/i915/i915_reg.h

2427

#define PRB0_TAIL _MMIO(0x2030)

sys/dev/drm/i915/i915_reg.h

2428

#define PRB0_HEAD _MMIO(0x2034)

sys/dev/drm/i915/i915_reg.h

2429

#define PRB0_START _MMIO(0x2038)

sys/dev/drm/i915/i915_reg.h

2430

#define PRB0_CTL _MMIO(0x203c)

sys/dev/drm/i915/i915_reg.h

2431

#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2432

#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2433

#define PRB1_START _MMIO(0x2048) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2434

#define PRB1_CTL _MMIO(0x204c) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2436

#define IPEIR_I965 _MMIO(0x2064)

sys/dev/drm/i915/i915_reg.h

2437

#define IPEHR_I965 _MMIO(0x2068)

sys/dev/drm/i915/i915_reg.h

2438

#define GEN7_SC_INSTDONE _MMIO(0x7100)

sys/dev/drm/i915/i915_reg.h

2439

#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)

sys/dev/drm/i915/i915_reg.h

2440

#define GEN7_ROW_INSTDONE _MMIO(0xe164)

sys/dev/drm/i915/i915_reg.h

2441

#define GEN8_MCR_SELECTOR _MMIO(0xfdc)

sys/dev/drm/i915/i915_reg.h

2450

#define RING_IPEIR(base) _MMIO((base) + 0x64)

sys/dev/drm/i915/i915_reg.h

2451

#define RING_IPEHR(base) _MMIO((base) + 0x68)

sys/dev/drm/i915/i915_reg.h

2457

#define RING_INSTDONE(base) _MMIO((base) + 0x6c)

sys/dev/drm/i915/i915_reg.h

2458

#define RING_INSTPS(base) _MMIO((base) + 0x70)

sys/dev/drm/i915/i915_reg.h

2459

#define RING_DMA_FADD(base) _MMIO((base) + 0x78)

sys/dev/drm/i915/i915_reg.h

2460

#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */

sys/dev/drm/i915/i915_reg.h

2461

#define RING_INSTPM(base) _MMIO((base) + 0xc0)

sys/dev/drm/i915/i915_reg.h

2462

#define RING_MI_MODE(base) _MMIO((base) + 0x9c)

sys/dev/drm/i915/i915_reg.h

2463

#define INSTPS _MMIO(0x2070) /* 965+ only */

sys/dev/drm/i915/i915_reg.h

2464

#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */

sys/dev/drm/i915/i915_reg.h

2465

#define ACTHD_I965 _MMIO(0x2074)

sys/dev/drm/i915/i915_reg.h

2466

#define HWS_PGA _MMIO(0x2080)

sys/dev/drm/i915/i915_reg.h

2469

#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */

sys/dev/drm/i915/i915_reg.h

2471

#define IPEIR _MMIO(0x2088)

sys/dev/drm/i915/i915_reg.h

2472

#define IPEHR _MMIO(0x208c)

sys/dev/drm/i915/i915_reg.h

2473

#define GEN2_INSTDONE _MMIO(0x2090)

sys/dev/drm/i915/i915_reg.h

2474

#define NOPID _MMIO(0x2094)

sys/dev/drm/i915/i915_reg.h

2475

#define HWSTAM _MMIO(0x2098)

sys/dev/drm/i915/i915_reg.h

2476

#define DMA_FADD_I8XX _MMIO(0x20d0)

sys/dev/drm/i915/i915_reg.h

2477

#define RING_BBSTATE(base) _MMIO((base) + 0x110)

sys/dev/drm/i915/i915_reg.h

2479

#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */

sys/dev/drm/i915/i915_reg.h

2480

#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */

sys/dev/drm/i915/i915_reg.h

2481

#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */

sys/dev/drm/i915/i915_reg.h

2482

#define RING_BBADDR(base) _MMIO((base) + 0x140)

sys/dev/drm/i915/i915_reg.h

2483

#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */

sys/dev/drm/i915/i915_reg.h

2484

#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */

sys/dev/drm/i915/i915_reg.h

2485

#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */

sys/dev/drm/i915/i915_reg.h

2486

#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */

sys/dev/drm/i915/i915_reg.h

2487

#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */

sys/dev/drm/i915/i915_reg.h

2489

#define ERROR_GEN6 _MMIO(0x40a0)

sys/dev/drm/i915/i915_reg.h

2490

#define GEN7_ERR_INT _MMIO(0x44040)

sys/dev/drm/i915/i915_reg.h

2502

#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)

sys/dev/drm/i915/i915_reg.h

2503

#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)

sys/dev/drm/i915/i915_reg.h

2507

#define FPGA_DBG _MMIO(0x42300)

sys/dev/drm/i915/i915_reg.h

2510

#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)

sys/dev/drm/i915/i915_reg.h

2515

#define DERRMR _MMIO(0x44050)

sys/dev/drm/i915/i915_reg.h

2539

#define _3D_CHICKEN _MMIO(0x2084)

sys/dev/drm/i915/i915_reg.h

2541

#define _3D_CHICKEN2 _MMIO(0x208c)

sys/dev/drm/i915/i915_reg.h

2543

#define FF_SLICE_CHICKEN _MMIO(0x2088)

sys/dev/drm/i915/i915_reg.h

2551

#define _3D_CHICKEN3 _MMIO(0x2090)

sys/dev/drm/i915/i915_reg.h

2559

#define MI_MODE _MMIO(0x209c)

sys/dev/drm/i915/i915_reg.h

2566

#define GEN6_GT_MODE _MMIO(0x20d0)

sys/dev/drm/i915/i915_reg.h

2567

#define GEN7_GT_MODE _MMIO(0x7008)

sys/dev/drm/i915/i915_reg.h

2578

#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)

sys/dev/drm/i915/i915_reg.h

2582

#define GEN8_STATE_ACK _MMIO(0x20F0)

sys/dev/drm/i915/i915_reg.h

2583

#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)

sys/dev/drm/i915/i915_reg.h

2584

#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)

sys/dev/drm/i915/i915_reg.h

2593

#define GFX_MODE _MMIO(0x2520)

sys/dev/drm/i915/i915_reg.h

2594

#define GFX_MODE_GEN7 _MMIO(0x229c)

sys/dev/drm/i915/i915_reg.h

2595

#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)

sys/dev/drm/i915/i915_reg.h

2616

#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)

sys/dev/drm/i915/i915_reg.h

2617

#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)

sys/dev/drm/i915/i915_reg.h

2618

#define SCPD0 _MMIO(0x209c) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2619

#define IER _MMIO(0x20a0)

sys/dev/drm/i915/i915_reg.h

2620

#define IIR _MMIO(0x20a4)

sys/dev/drm/i915/i915_reg.h

2621

#define IMR _MMIO(0x20a8)

sys/dev/drm/i915/i915_reg.h

2622

#define ISR _MMIO(0x20ac)

sys/dev/drm/i915/i915_reg.h

2623

#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)

sys/dev/drm/i915/i915_reg.h

2626

#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)

sys/dev/drm/i915/i915_reg.h

2627

#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)

sys/dev/drm/i915/i915_reg.h

2628

#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)

sys/dev/drm/i915/i915_reg.h

2629

#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)

sys/dev/drm/i915/i915_reg.h

2630

#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)

sys/dev/drm/i915/i915_reg.h

2631

#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)

sys/dev/drm/i915/i915_reg.h

2632

#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)

sys/dev/drm/i915/i915_reg.h

2636

#define EIR _MMIO(0x20b0)

sys/dev/drm/i915/i915_reg.h

2637

#define EMR _MMIO(0x20b4)

sys/dev/drm/i915/i915_reg.h

2638

#define ESR _MMIO(0x20b8)

sys/dev/drm/i915/i915_reg.h

2645

#define INSTPM _MMIO(0x20c0)

sys/dev/drm/i915/i915_reg.h

2653

#define ACTHD _MMIO(0x20c8)

sys/dev/drm/i915/i915_reg.h

2654

#define MEM_MODE _MMIO(0x20cc)

sys/dev/drm/i915/i915_reg.h

2658

#define FW_BLC _MMIO(0x20d8)

sys/dev/drm/i915/i915_reg.h

2659

#define FW_BLC2 _MMIO(0x20dc)

sys/dev/drm/i915/i915_reg.h

2660

#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2668

#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2670

#define MBUS_ABOX_CTL _MMIO(0x45038)

sys/dev/drm/i915/i915_reg.h

2691

#define MBUS_UBOX_CTL _MMIO(0x4503C)

sys/dev/drm/i915/i915_reg.h

2692

#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)

sys/dev/drm/i915/i915_reg.h

2693

#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)

sys/dev/drm/i915/i915_reg.h

2757

#define MI_STATE _MMIO(0x20e4) /* gen2 only */

sys/dev/drm/i915/i915_reg.h

2761

#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2770

#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */

sys/dev/drm/i915/i915_reg.h

2771

#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)

sys/dev/drm/i915/i915_reg.h

2773

#define ECOSKPD _MMIO(0x21d0)

sys/dev/drm/i915/i915_reg.h

2777

#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */

sys/dev/drm/i915/i915_reg.h

2780

#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */

sys/dev/drm/i915/i915_reg.h

2785

#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)

sys/dev/drm/i915/i915_reg.h

2789

#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)

sys/dev/drm/i915/i915_reg.h

2794

#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)

sys/dev/drm/i915/i915_reg.h

2795

#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)

sys/dev/drm/i915/i915_reg.h

2798

#define HSW_PAVP_FUSE1 _MMIO(0x911C)

sys/dev/drm/i915/i915_reg.h

2805

#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)

sys/dev/drm/i915/i915_reg.h

2817

#define GEN8_FUSE2 _MMIO(0x9120)

sys/dev/drm/i915/i915_reg.h

2831

#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)

sys/dev/drm/i915/i915_reg.h

2835

#define GEN8_EU_DISABLE0 _MMIO(0x9134)

sys/dev/drm/i915/i915_reg.h

2840

#define GEN8_EU_DISABLE1 _MMIO(0x9138)

sys/dev/drm/i915/i915_reg.h

2845

#define GEN8_EU_DISABLE2 _MMIO(0x913c)

sys/dev/drm/i915/i915_reg.h

2848

#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)

sys/dev/drm/i915/i915_reg.h

2850

#define GEN10_EU_DISABLE3 _MMIO(0x9140)

sys/dev/drm/i915/i915_reg.h

2853

#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)

sys/dev/drm/i915/i915_reg.h

2858

#define GEN11_EU_DISABLE _MMIO(0x9134)

sys/dev/drm/i915/i915_reg.h

2861

#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)

sys/dev/drm/i915/i915_reg.h

2864

#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)

sys/dev/drm/i915/i915_reg.h

2866

#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)

sys/dev/drm/i915/i915_reg.h

289

#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)

sys/dev/drm/i915/i915_reg.h

2947

#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)

sys/dev/drm/i915/i915_reg.h

2959

#define GEN6_BSD_RNCID _MMIO(0x12198)

sys/dev/drm/i915/i915_reg.h

296

#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */

sys/dev/drm/i915/i915_reg.h

2961

#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)

sys/dev/drm/i915/i915_reg.h

2982

#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */

sys/dev/drm/i915/i915_reg.h

2983

#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */

sys/dev/drm/i915/i915_reg.h

2984

#define FBC_CONTROL _MMIO(0x3208)

sys/dev/drm/i915/i915_reg.h

2992

#define FBC_COMMAND _MMIO(0x320c)

sys/dev/drm/i915/i915_reg.h

2994

#define FBC_STATUS _MMIO(0x3210)

sys/dev/drm/i915/i915_reg.h

2999

#define FBC_CONTROL2 _MMIO(0x3214)

sys/dev/drm/i915/i915_reg.h

3007

#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */

sys/dev/drm/i915/i915_reg.h

3008

#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

3012

#define FBC_LLC_READ_CTRL _MMIO(0x9044)

sys/dev/drm/i915/i915_reg.h

3016

#define DPFC_CB_BASE _MMIO(0x3200)

sys/dev/drm/i915/i915_reg.h

3017

#define DPFC_CONTROL _MMIO(0x3208)

sys/dev/drm/i915/i915_reg.h

3028

#define DPFC_RECOMP_CTL _MMIO(0x320c)

sys/dev/drm/i915/i915_reg.h

3034

#define DPFC_STATUS _MMIO(0x3210)

sys/dev/drm/i915/i915_reg.h

3039

#define DPFC_STATUS2 _MMIO(0x3214)

sys/dev/drm/i915/i915_reg.h

304

#define VLV_G3DCTL _MMIO(0x9024)

sys/dev/drm/i915/i915_reg.h

3040

#define DPFC_FENCE_YOFF _MMIO(0x3218)

sys/dev/drm/i915/i915_reg.h

3041

#define DPFC_CHICKEN _MMIO(0x3224)

sys/dev/drm/i915/i915_reg.h

3045

#define ILK_DPFC_CB_BASE _MMIO(0x43200)

sys/dev/drm/i915/i915_reg.h

3046

#define ILK_DPFC_CONTROL _MMIO(0x43208)

sys/dev/drm/i915/i915_reg.h

305

#define VLV_GSCKGCTL _MMIO(0x9028)

sys/dev/drm/i915/i915_reg.h

3050

#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)

sys/dev/drm/i915/i915_reg.h

3051

#define ILK_DPFC_STATUS _MMIO(0x43210)

sys/dev/drm/i915/i915_reg.h

3053

#define IVB_FBC_STATUS2 _MMIO(0x43214)

sys/dev/drm/i915/i915_reg.h

3056

#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)

sys/dev/drm/i915/i915_reg.h

3057

#define ILK_DPFC_CHICKEN _MMIO(0x43224)

sys/dev/drm/i915/i915_reg.h

3060

#define ILK_FBC_RT_BASE _MMIO(0x2128)

sys/dev/drm/i915/i915_reg.h

3064

#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)

sys/dev/drm/i915/i915_reg.h

307

#define GEN6_MBCTL _MMIO(0x0907c)

sys/dev/drm/i915/i915_reg.h

3074

#define SNB_DPFC_CTL_SA _MMIO(0x100100)

sys/dev/drm/i915/i915_reg.h

3076

#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)

sys/dev/drm/i915/i915_reg.h

3079

#define IVB_FBC_RT_BASE _MMIO(0x7020)

sys/dev/drm/i915/i915_reg.h

3081

#define IPS_CTL _MMIO(0x43408)

sys/dev/drm/i915/i915_reg.h

3084

#define MSG_FBC_REND_STATE _MMIO(0x50380)

sys/dev/drm/i915/i915_reg.h

3091

#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \

sys/dev/drm/i915/i915_reg.h

3109

#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */

sys/dev/drm/i915/i915_reg.h

3136

#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */

sys/dev/drm/i915/i915_reg.h

314

#define GEN6_GDRST _MMIO(0x941c)

sys/dev/drm/i915/i915_reg.h

3151

#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */

sys/dev/drm/i915/i915_reg.h

3159

#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */

sys/dev/drm/i915/i915_reg.h

3160

#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */

sys/dev/drm/i915/i915_reg.h

3166

#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */

sys/dev/drm/i915/i915_reg.h

3177

#define VGA0 _MMIO(0x6000)

sys/dev/drm/i915/i915_reg.h

3178

#define VGA1 _MMIO(0x6004)

sys/dev/drm/i915/i915_reg.h

3179

#define VGA_PD _MMIO(0x6010)

sys/dev/drm/i915/i915_reg.h

3215

#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)

sys/dev/drm/i915/i915_reg.h

3217

#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)

sys/dev/drm/i915/i915_reg.h

3228

#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)

sys/dev/drm/i915/i915_reg.h

3313

#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)

sys/dev/drm/i915/i915_reg.h

3329

#define DPLL_TEST _MMIO(0x606c)

sys/dev/drm/i915/i915_reg.h

334

#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)

sys/dev/drm/i915/i915_reg.h

3340

#define D_STATE _MMIO(0x6104)

sys/dev/drm/i915/i915_reg.h

3345

#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)

sys/dev/drm/i915/i915_reg.h

335

#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)

sys/dev/drm/i915/i915_reg.h

336

#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220)

sys/dev/drm/i915/i915_reg.h

3385

#define RENCLK_GATE_D1 _MMIO(0x6204)

sys/dev/drm/i915/i915_reg.h

339

#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)

sys/dev/drm/i915/i915_reg.h

340

#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)

sys/dev/drm/i915/i915_reg.h

342

#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)

sys/dev/drm/i915/i915_reg.h

3449

#define RENCLK_GATE_D2 _MMIO(0x6208)

sys/dev/drm/i915/i915_reg.h

3454

#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */

sys/dev/drm/i915/i915_reg.h

3457

#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */

sys/dev/drm/i915/i915_reg.h

3458

#define DEUC _MMIO(0x6214) /* CRL only */

sys/dev/drm/i915/i915_reg.h

3460

#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)

sys/dev/drm/i915/i915_reg.h

3463

#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)

sys/dev/drm/i915/i915_reg.h

3465

#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)

sys/dev/drm/i915/i915_reg.h

3470

#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)

sys/dev/drm/i915/i915_reg.h

3477

#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)

sys/dev/drm/i915/i915_reg.h

3485

#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \

sys/dev/drm/i915/i915_reg.h

3504

#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)

sys/dev/drm/i915/i915_reg.h

3505

#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)

sys/dev/drm/i915/i915_reg.h

3511

#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)

sys/dev/drm/i915/i915_reg.h

3514

#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)

sys/dev/drm/i915/i915_reg.h

3521

#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)

sys/dev/drm/i915/i915_reg.h

3525

#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)

sys/dev/drm/i915/i915_reg.h

3529

#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)

sys/dev/drm/i915/i915_reg.h

3530

#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)

sys/dev/drm/i915/i915_reg.h

3533

#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)

sys/dev/drm/i915/i915_reg.h

3534

#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)

sys/dev/drm/i915/i915_reg.h

3535

#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)

sys/dev/drm/i915/i915_reg.h

3555

#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)

sys/dev/drm/i915/i915_reg.h

3559

#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)

sys/dev/drm/i915/i915_reg.h

3562

#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)

sys/dev/drm/i915/i915_reg.h

357

#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)

sys/dev/drm/i915/i915_reg.h

3582

#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)

sys/dev/drm/i915/i915_reg.h

3583

#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)

sys/dev/drm/i915/i915_reg.h

3585

#define TSC1 _MMIO(0x11001)

sys/dev/drm/i915/i915_reg.h

3587

#define TR1 _MMIO(0x11006)

sys/dev/drm/i915/i915_reg.h

3588

#define TSFS _MMIO(0x11020)

sys/dev/drm/i915/i915_reg.h

3593

#define CRSTANDVID _MMIO(0x11100)

sys/dev/drm/i915/i915_reg.h

3594

#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */

sys/dev/drm/i915/i915_reg.h

3597

#define VIDFREQ_BASE _MMIO(0x11110)

sys/dev/drm/i915/i915_reg.h

3598

#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */

sys/dev/drm/i915/i915_reg.h

3599

#define VIDFREQ2 _MMIO(0x11114)

sys/dev/drm/i915/i915_reg.h

3600

#define VIDFREQ3 _MMIO(0x11118)

sys/dev/drm/i915/i915_reg.h

3601

#define VIDFREQ4 _MMIO(0x1111c)

sys/dev/drm/i915/i915_reg.h

3613

#define INTTOEXT_BASE_ILK _MMIO(0x11300)

sys/dev/drm/i915/i915_reg.h

3614

#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */

sys/dev/drm/i915/i915_reg.h

3623

#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */

sys/dev/drm/i915/i915_reg.h

3638

#define MEMIHYST _MMIO(0x1117c)

sys/dev/drm/i915/i915_reg.h

3639

#define MEMINTREN _MMIO(0x11180) /* 16 bits */

sys/dev/drm/i915/i915_reg.h

3649

#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */

sys/dev/drm/i915/i915_reg.h

3669

#define MEMINTRSTS _MMIO(0x11184)

sys/dev/drm/i915/i915_reg.h

3678

#define MEMMODECTL _MMIO(0x11190)

sys/dev/drm/i915/i915_reg.h

3695

#define RCBMAXAVG _MMIO(0x1119c)

sys/dev/drm/i915/i915_reg.h

3696

#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */

sys/dev/drm/i915/i915_reg.h

3708

#define MEMSTAT_CTG _MMIO(0x111a0)

sys/dev/drm/i915/i915_reg.h

3709

#define RCBMINAVG _MMIO(0x111a0)

sys/dev/drm/i915/i915_reg.h

3710

#define RCUPEI _MMIO(0x111b0)

sys/dev/drm/i915/i915_reg.h

3711

#define RCDNEI _MMIO(0x111b4)

sys/dev/drm/i915/i915_reg.h

3712

#define RSTDBYCTL _MMIO(0x111b8)

sys/dev/drm/i915/i915_reg.h

3756

#define VIDCTL _MMIO(0x111c0)

sys/dev/drm/i915/i915_reg.h

3757

#define VIDSTS _MMIO(0x111c8)

sys/dev/drm/i915/i915_reg.h

3758

#define VIDSTART _MMIO(0x111cc) /* 8 bits */

sys/dev/drm/i915/i915_reg.h

3759

#define MEMSTAT_ILK _MMIO(0x111f8)

sys/dev/drm/i915/i915_reg.h

3770

#define RCPREVBSYTUPAVG _MMIO(0x113b8)

sys/dev/drm/i915/i915_reg.h

3771

#define RCPREVBSYTDNAVG _MMIO(0x113bc)

sys/dev/drm/i915/i915_reg.h

3772

#define PMMISC _MMIO(0x11214)

sys/dev/drm/i915/i915_reg.h

3774

#define SDEW _MMIO(0x1124c)

sys/dev/drm/i915/i915_reg.h

3775

#define CSIEW0 _MMIO(0x11250)

sys/dev/drm/i915/i915_reg.h

3776

#define CSIEW1 _MMIO(0x11254)

sys/dev/drm/i915/i915_reg.h

3777

#define CSIEW2 _MMIO(0x11258)

sys/dev/drm/i915/i915_reg.h

3778

#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */

sys/dev/drm/i915/i915_reg.h

3779

#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */

sys/dev/drm/i915/i915_reg.h

3780

#define MCHAFE _MMIO(0x112c0)

sys/dev/drm/i915/i915_reg.h

3781

#define CSIEC _MMIO(0x112e0)

sys/dev/drm/i915/i915_reg.h

3782

#define DMIEC _MMIO(0x112e4)

sys/dev/drm/i915/i915_reg.h

3783

#define DDREC _MMIO(0x112e8)

sys/dev/drm/i915/i915_reg.h

3784

#define PEG0EC _MMIO(0x112ec)

sys/dev/drm/i915/i915_reg.h

3785

#define PEG1EC _MMIO(0x112f0)

sys/dev/drm/i915/i915_reg.h

3786

#define GFXEC _MMIO(0x112f4)

sys/dev/drm/i915/i915_reg.h

3787

#define RPPREVBSYTUPAVG _MMIO(0x113b8)

sys/dev/drm/i915/i915_reg.h

3788

#define RPPREVBSYTDNAVG _MMIO(0x113bc)

sys/dev/drm/i915/i915_reg.h

3789

#define ECR _MMIO(0x11600)

sys/dev/drm/i915/i915_reg.h

379

#define GAM_ECOCHK _MMIO(0x4090)

sys/dev/drm/i915/i915_reg.h

3793

#define OGW0 _MMIO(0x11608)

sys/dev/drm/i915/i915_reg.h

3794

#define OGW1 _MMIO(0x1160c)

sys/dev/drm/i915/i915_reg.h

3795

#define EG0 _MMIO(0x11610)

sys/dev/drm/i915/i915_reg.h

3796

#define EG1 _MMIO(0x11614)

sys/dev/drm/i915/i915_reg.h

3797

#define EG2 _MMIO(0x11618)

sys/dev/drm/i915/i915_reg.h

3798

#define EG3 _MMIO(0x1161c)

sys/dev/drm/i915/i915_reg.h

3799

#define EG4 _MMIO(0x11620)

sys/dev/drm/i915/i915_reg.h

3800

#define EG5 _MMIO(0x11624)

sys/dev/drm/i915/i915_reg.h

3801

#define EG6 _MMIO(0x11628)

sys/dev/drm/i915/i915_reg.h

3802

#define EG7 _MMIO(0x1162c)

sys/dev/drm/i915/i915_reg.h

3803

#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */

sys/dev/drm/i915/i915_reg.h

3804

#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */

sys/dev/drm/i915/i915_reg.h

3805

#define LCFUSE02 _MMIO(0x116c0)

sys/dev/drm/i915/i915_reg.h

3807

#define CSIPLL0 _MMIO(0x12c10)

sys/dev/drm/i915/i915_reg.h

3808

#define DDRMPLL1 _MMIO(0X12c20)

sys/dev/drm/i915/i915_reg.h

3809

#define PEG_BAND_GAP_DATA _MMIO(0x14d68)

sys/dev/drm/i915/i915_reg.h

3811

#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)

sys/dev/drm/i915/i915_reg.h

3814

#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)

sys/dev/drm/i915/i915_reg.h

3815

#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)

sys/dev/drm/i915/i915_reg.h

3816

#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)

sys/dev/drm/i915/i915_reg.h

3817

#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)

sys/dev/drm/i915/i915_reg.h

3818

#define BXT_RP_STATE_CAP _MMIO(0x138170)

sys/dev/drm/i915/i915_reg.h

3848

#define CCID _MMIO(0x2180)

sys/dev/drm/i915/i915_reg.h

3865

#define CXT_SIZE _MMIO(0x21a0)

sys/dev/drm/i915/i915_reg.h

3874

#define GEN7_CXT_SIZE _MMIO(0x21a8)

sys/dev/drm/i915/i915_reg.h

3914

#define CHV_CLK_CTL1 _MMIO(0x101100)

sys/dev/drm/i915/i915_reg.h

3915

#define VLV_CLK_CTL2 _MMIO(0x101104)

sys/dev/drm/i915/i915_reg.h

392

#define GAC_ECO_BITS _MMIO(0x14090)

sys/dev/drm/i915/i915_reg.h

3922

#define OVADD _MMIO(0x30000)

sys/dev/drm/i915/i915_reg.h

3923

#define DOVSTA _MMIO(0x30008)

sys/dev/drm/i915/i915_reg.h

3925

#define OGAMC5 _MMIO(0x30010)

sys/dev/drm/i915/i915_reg.h

3926

#define OGAMC4 _MMIO(0x30014)

sys/dev/drm/i915/i915_reg.h

3927

#define OGAMC3 _MMIO(0x30018)

sys/dev/drm/i915/i915_reg.h

3928

#define OGAMC2 _MMIO(0x3001c)

sys/dev/drm/i915/i915_reg.h

3929

#define OGAMC1 _MMIO(0x30020)

sys/dev/drm/i915/i915_reg.h

3930

#define OGAMC0 _MMIO(0x30024)

sys/dev/drm/i915/i915_reg.h

3935

#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)

sys/dev/drm/i915/i915_reg.h

3940

#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)

sys/dev/drm/i915/i915_reg.h

3959

#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)

sys/dev/drm/i915/i915_reg.h

3964

#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)

sys/dev/drm/i915/i915_reg.h

3967

#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)

sys/dev/drm/i915/i915_reg.h

397

#define GAB_CTL _MMIO(0x24000)

sys/dev/drm/i915/i915_reg.h

3970

#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)

sys/dev/drm/i915/i915_reg.h

400

#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)

sys/dev/drm/i915/i915_reg.h

4074

#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \

sys/dev/drm/i915/i915_reg.h

4128

#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)

sys/dev/drm/i915/i915_reg.h

4154

#define EDP_PSR_IMR _MMIO(0x64834)

sys/dev/drm/i915/i915_reg.h

4155

#define EDP_PSR_IIR _MMIO(0x64838)

sys/dev/drm/i915/i915_reg.h

4160

#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)

sys/dev/drm/i915/i915_reg.h

4167

#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */

sys/dev/drm/i915/i915_reg.h

4169

#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)

sys/dev/drm/i915/i915_reg.h

4194

#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)

sys/dev/drm/i915/i915_reg.h

4197

#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */

sys/dev/drm/i915/i915_reg.h

4205

#define EDP_PSR2_CTL _MMIO(0x6f900)

sys/dev/drm/i915/i915_reg.h

424

#define _VGA_MSR_WRITE _MMIO(0x3c2)

sys/dev/drm/i915/i915_reg.h

4246

#define EDP_PSR2_STATUS _MMIO(0x6f940)

sys/dev/drm/i915/i915_reg.h

4251

#define ADPA _MMIO(0x61100)

sys/dev/drm/i915/i915_reg.h

4252

#define PCH_ADPA _MMIO(0xe1100)

sys/dev/drm/i915/i915_reg.h

4253

#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)

sys/dev/drm/i915/i915_reg.h

4300

#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)

sys/dev/drm/i915/i915_reg.h

4330

#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)

sys/dev/drm/i915/i915_reg.h

4398

#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)

sys/dev/drm/i915/i915_reg.h

4399

#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)

sys/dev/drm/i915/i915_reg.h

4402

#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)

sys/dev/drm/i915/i915_reg.h

4403

#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)

sys/dev/drm/i915/i915_reg.h

4404

#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)

sys/dev/drm/i915/i915_reg.h

4405

#define PCH_SDVOB _MMIO(0xe1140)

sys/dev/drm/i915/i915_reg.h

4407

#define PCH_HDMIC _MMIO(0xe1150)

sys/dev/drm/i915/i915_reg.h

4408

#define PCH_HDMID _MMIO(0xe1160)

sys/dev/drm/i915/i915_reg.h

4410

#define PORT_DFT_I9XX _MMIO(0x61150)

sys/dev/drm/i915/i915_reg.h

4412

#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)

sys/dev/drm/i915/i915_reg.h

4475

#define DVOA _MMIO(_DVOA)

sys/dev/drm/i915/i915_reg.h

4477

#define DVOB _MMIO(_DVOB)

sys/dev/drm/i915/i915_reg.h

4479

#define DVOC _MMIO(_DVOC)

sys/dev/drm/i915/i915_reg.h

4506

#define DVOA_SRCDIM _MMIO(0x61124)

sys/dev/drm/i915/i915_reg.h

4507

#define DVOB_SRCDIM _MMIO(0x61144)

sys/dev/drm/i915/i915_reg.h

4508

#define DVOC_SRCDIM _MMIO(0x61164)

sys/dev/drm/i915/i915_reg.h

4513

#define LVDS _MMIO(0x61180)

sys/dev/drm/i915/i915_reg.h

4566

#define VIDEO_DIP_DATA _MMIO(0x61178)

sys/dev/drm/i915/i915_reg.h

4572

#define VIDEO_DIP_CTL _MMIO(0x61170)

sys/dev/drm/i915/i915_reg.h

4613

#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \

sys/dev/drm/i915/i915_reg.h

462

#define MI_PREDICATE_SRC0 _MMIO(0x2400)

sys/dev/drm/i915/i915_reg.h

463

#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)

sys/dev/drm/i915/i915_reg.h

464

#define MI_PREDICATE_SRC1 _MMIO(0x2408)

sys/dev/drm/i915/i915_reg.h

465

#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)

sys/dev/drm/i915/i915_reg.h

467

#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)

sys/dev/drm/i915/i915_reg.h

4686

#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)

sys/dev/drm/i915/i915_reg.h

4704

#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)

sys/dev/drm/i915/i915_reg.h

4716

#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)

sys/dev/drm/i915/i915_reg.h

4734

#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */

sys/dev/drm/i915/i915_reg.h

474

#define BCS_SWCTRL _MMIO(0x22200)

sys/dev/drm/i915/i915_reg.h

4757

#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)

sys/dev/drm/i915/i915_reg.h

476

#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)

sys/dev/drm/i915/i915_reg.h

477

#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)

sys/dev/drm/i915/i915_reg.h

4779

#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)

sys/dev/drm/i915/i915_reg.h

478

#define HS_INVOCATION_COUNT _MMIO(0x2300)

sys/dev/drm/i915/i915_reg.h

4784

#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)

sys/dev/drm/i915/i915_reg.h

4785

#define BLC_PWM_CPU_CTL _MMIO(0x48254)

sys/dev/drm/i915/i915_reg.h

4787

#define HSW_BLC_PWM2_CTL _MMIO(0x48350)

sys/dev/drm/i915/i915_reg.h

479

#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)

sys/dev/drm/i915/i915_reg.h

4791

#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)

sys/dev/drm/i915/i915_reg.h

4795

#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)

sys/dev/drm/i915/i915_reg.h

4797

#define UTIL_PIN_CTL _MMIO(0x48400)

sys/dev/drm/i915/i915_reg.h

480

#define DS_INVOCATION_COUNT _MMIO(0x2308)

sys/dev/drm/i915/i915_reg.h

481

#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)

sys/dev/drm/i915/i915_reg.h

482

#define IA_VERTICES_COUNT _MMIO(0x2310)

sys/dev/drm/i915/i915_reg.h

4824

#define PCH_GTC_CTL _MMIO(0xe7000)

sys/dev/drm/i915/i915_reg.h

4828

#define TV_CTL _MMIO(0x68000)

sys/dev/drm/i915/i915_reg.h

483

#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)

sys/dev/drm/i915/i915_reg.h

484

#define IA_PRIMITIVES_COUNT _MMIO(0x2318)

sys/dev/drm/i915/i915_reg.h

485

#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)

sys/dev/drm/i915/i915_reg.h

486

#define VS_INVOCATION_COUNT _MMIO(0x2320)

sys/dev/drm/i915/i915_reg.h

487

#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)

sys/dev/drm/i915/i915_reg.h

488

#define GS_INVOCATION_COUNT _MMIO(0x2328)

sys/dev/drm/i915/i915_reg.h

489

#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)

sys/dev/drm/i915/i915_reg.h

4897

#define TV_DAC _MMIO(0x68004)

sys/dev/drm/i915/i915_reg.h

490

#define GS_PRIMITIVES_COUNT _MMIO(0x2330)

sys/dev/drm/i915/i915_reg.h

491

#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)

sys/dev/drm/i915/i915_reg.h

492

#define CL_INVOCATION_COUNT _MMIO(0x2338)

sys/dev/drm/i915/i915_reg.h

493

#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)

sys/dev/drm/i915/i915_reg.h

494

#define CL_PRIMITIVES_COUNT _MMIO(0x2340)

sys/dev/drm/i915/i915_reg.h

4948

#define TV_CSC_Y _MMIO(0x68010)

sys/dev/drm/i915/i915_reg.h

495

#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)

sys/dev/drm/i915/i915_reg.h

4954

#define TV_CSC_Y2 _MMIO(0x68014)

sys/dev/drm/i915/i915_reg.h

496

#define PS_INVOCATION_COUNT _MMIO(0x2348)

sys/dev/drm/i915/i915_reg.h

4965

#define TV_CSC_U _MMIO(0x68018)

sys/dev/drm/i915/i915_reg.h

497

#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)

sys/dev/drm/i915/i915_reg.h

4971

#define TV_CSC_U2 _MMIO(0x6801c)

sys/dev/drm/i915/i915_reg.h

498

#define PS_DEPTH_COUNT _MMIO(0x2350)

sys/dev/drm/i915/i915_reg.h

4982

#define TV_CSC_V _MMIO(0x68020)

sys/dev/drm/i915/i915_reg.h

4988

#define TV_CSC_V2 _MMIO(0x68024)

sys/dev/drm/i915/i915_reg.h

499

#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)

sys/dev/drm/i915/i915_reg.h

4999

#define TV_CLR_KNOBS _MMIO(0x68028)

sys/dev/drm/i915/i915_reg.h

5013

#define TV_CLR_LEVEL _MMIO(0x6802c)

sys/dev/drm/i915/i915_reg.h

502

#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)

sys/dev/drm/i915/i915_reg.h

5021

#define TV_H_CTL_1 _MMIO(0x68030)

sys/dev/drm/i915/i915_reg.h

5029

#define TV_H_CTL_2 _MMIO(0x68034)

sys/dev/drm/i915/i915_reg.h

503

#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)

sys/dev/drm/i915/i915_reg.h

5039

#define TV_H_CTL_3 _MMIO(0x68038)

sys/dev/drm/i915/i915_reg.h

5047

#define TV_V_CTL_1 _MMIO(0x6803c)

sys/dev/drm/i915/i915_reg.h

505

#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)

sys/dev/drm/i915/i915_reg.h

5058

#define TV_V_CTL_2 _MMIO(0x68040)

sys/dev/drm/i915/i915_reg.h

506

#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)

sys/dev/drm/i915/i915_reg.h

5074

#define TV_V_CTL_3 _MMIO(0x68044)

sys/dev/drm/i915/i915_reg.h

508

#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)

sys/dev/drm/i915/i915_reg.h

509

#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)

sys/dev/drm/i915/i915_reg.h

5092

#define TV_V_CTL_4 _MMIO(0x68048)

sys/dev/drm/i915/i915_reg.h

510

#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)

sys/dev/drm/i915/i915_reg.h

5106

#define TV_V_CTL_5 _MMIO(0x6804c)

sys/dev/drm/i915/i915_reg.h

511

#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)

sys/dev/drm/i915/i915_reg.h

512

#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)

sys/dev/drm/i915/i915_reg.h

5120

#define TV_V_CTL_6 _MMIO(0x68050)

sys/dev/drm/i915/i915_reg.h

513

#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)

sys/dev/drm/i915/i915_reg.h

5134

#define TV_V_CTL_7 _MMIO(0x68054)

sys/dev/drm/i915/i915_reg.h

5148

#define TV_SC_CTL_1 _MMIO(0x68060)

sys/dev/drm/i915/i915_reg.h

515

#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)

sys/dev/drm/i915/i915_reg.h

516

#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)

sys/dev/drm/i915/i915_reg.h

517

#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)

sys/dev/drm/i915/i915_reg.h

5170

#define TV_SC_CTL_2 _MMIO(0x68064)

sys/dev/drm/i915/i915_reg.h

5178

#define TV_SC_CTL_3 _MMIO(0x68068)

sys/dev/drm/i915/i915_reg.h

5186

#define TV_WIN_POS _MMIO(0x68070)

sys/dev/drm/i915/i915_reg.h

5194

#define TV_WIN_SIZE _MMIO(0x68074)

sys/dev/drm/i915/i915_reg.h

520

#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)

sys/dev/drm/i915/i915_reg.h

5206

#define TV_FILTER_CTL_1 _MMIO(0x68080)

sys/dev/drm/i915/i915_reg.h

521

#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)

sys/dev/drm/i915/i915_reg.h

523

#define GEN7_OACONTROL _MMIO(0x2360)

sys/dev/drm/i915/i915_reg.h

5239

#define TV_FILTER_CTL_2 _MMIO(0x68084)

sys/dev/drm/i915/i915_reg.h

5255

#define TV_FILTER_CTL_3 _MMIO(0x68088)

sys/dev/drm/i915/i915_reg.h

5275

#define TV_CC_CONTROL _MMIO(0x68090)

sys/dev/drm/i915/i915_reg.h

5291

#define TV_CC_DATA _MMIO(0x68094)

sys/dev/drm/i915/i915_reg.h

5300

#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */

sys/dev/drm/i915/i915_reg.h

5301

#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */

sys/dev/drm/i915/i915_reg.h

5302

#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */

sys/dev/drm/i915/i915_reg.h

5303

#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */

sys/dev/drm/i915/i915_reg.h

5306

#define DP_A _MMIO(0x64000) /* eDP */

sys/dev/drm/i915/i915_reg.h

5307

#define DP_B _MMIO(0x64100)

sys/dev/drm/i915/i915_reg.h

5308

#define DP_C _MMIO(0x64200)

sys/dev/drm/i915/i915_reg.h

5309

#define DP_D _MMIO(0x64300)

sys/dev/drm/i915/i915_reg.h

5311

#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)

sys/dev/drm/i915/i915_reg.h

5312

#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)

sys/dev/drm/i915/i915_reg.h

5313

#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)

sys/dev/drm/i915/i915_reg.h

540

#define GEN8_OACTXID _MMIO(0x2364)

sys/dev/drm/i915/i915_reg.h

542

#define GEN8_OA_DEBUG _MMIO(0x2B04)

sys/dev/drm/i915/i915_reg.h

5446

#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */

sys/dev/drm/i915/i915_reg.h

548

#define GEN8_OACONTROL _MMIO(0x2B00)

sys/dev/drm/i915/i915_reg.h

557

#define GEN8_OACTXCONTROL _MMIO(0x2360)

sys/dev/drm/i915/i915_reg.h

563

#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */

sys/dev/drm/i915/i915_reg.h

5643

#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \

sys/dev/drm/i915/i915_reg.h

5668

#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)

sys/dev/drm/i915/i915_reg.h

5689

#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */

sys/dev/drm/i915/i915_reg.h

569

#define GEN8_OABUFFER_UDW _MMIO(0x23b4)

sys/dev/drm/i915/i915_reg.h

570

#define GEN8_OABUFFER _MMIO(0x2b14)

sys/dev/drm/i915/i915_reg.h

5719

#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)

sys/dev/drm/i915/i915_reg.h

573

#define GEN7_OASTATUS1 _MMIO(0x2364)

sys/dev/drm/i915/i915_reg.h

5734

#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */

sys/dev/drm/i915/i915_reg.h

5747

#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */

sys/dev/drm/i915/i915_reg.h

5754

#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)

sys/dev/drm/i915/i915_reg.h

5765

#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)

sys/dev/drm/i915/i915_reg.h

5781

#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)

sys/dev/drm/i915/i915_reg.h

579

#define GEN7_OASTATUS2 _MMIO(0x2368)

sys/dev/drm/i915/i915_reg.h

5792

#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)

sys/dev/drm/i915/i915_reg.h

5799

#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)

sys/dev/drm/i915/i915_reg.h

5808

#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)

sys/dev/drm/i915/i915_reg.h

5811

#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)

sys/dev/drm/i915/i915_reg.h

5812

#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */

sys/dev/drm/i915/i915_reg.h

5821

#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)

sys/dev/drm/i915/i915_reg.h

583

#define GEN8_OASTATUS _MMIO(0x2b08)

sys/dev/drm/i915/i915_reg.h

5830

#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */

sys/dev/drm/i915/i915_reg.h

5841

#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)

sys/dev/drm/i915/i915_reg.h

5862

#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)

sys/dev/drm/i915/i915_reg.h

5885

#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))

sys/dev/drm/i915/i915_reg.h

589

#define GEN8_OAHEADPTR _MMIO(0x2B0C)

sys/dev/drm/i915/i915_reg.h

5893

#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)

sys/dev/drm/i915/i915_reg.h

5897

#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)

sys/dev/drm/i915/i915_reg.h

591

#define GEN8_OATAILPTR _MMIO(0x2B10)

sys/dev/drm/i915/i915_reg.h

5952

#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))

sys/dev/drm/i915/i915_reg.h

5960

_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))

sys/dev/drm/i915/i915_reg.h

5966

_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))

sys/dev/drm/i915/i915_reg.h

5969

#define WM0_PIPEA_ILK _MMIO(0x45100)

sys/dev/drm/i915/i915_reg.h

5976

#define WM0_PIPEB_ILK _MMIO(0x45104)

sys/dev/drm/i915/i915_reg.h

5977

#define WM0_PIPEC_IVB _MMIO(0x45200)

sys/dev/drm/i915/i915_reg.h

5978

#define WM1_LP_ILK _MMIO(0x45108)

sys/dev/drm/i915/i915_reg.h

5988

#define WM2_LP_ILK _MMIO(0x4510c)

sys/dev/drm/i915/i915_reg.h

5990

#define WM3_LP_ILK _MMIO(0x45110)

sys/dev/drm/i915/i915_reg.h

5992

#define WM1S_LP_ILK _MMIO(0x45120)

sys/dev/drm/i915/i915_reg.h

5993

#define WM2S_LP_IVB _MMIO(0x45124)

sys/dev/drm/i915/i915_reg.h

5994

#define WM3S_LP_IVB _MMIO(0x45128)

sys/dev/drm/i915/i915_reg.h

6002

#define MLTR_ILK _MMIO(0x11222)

sys/dev/drm/i915/i915_reg.h

6010

#define SSKPD _MMIO(0x5d10)

sys/dev/drm/i915/i915_reg.h

607

#define EU_PERF_CNTL0 _MMIO(0xe458)

sys/dev/drm/i915/i915_reg.h

608

#define EU_PERF_CNTL1 _MMIO(0xe558)

sys/dev/drm/i915/i915_reg.h

6082

#define CURSIZE _MMIO(0x700a0) /* 845/865 */

sys/dev/drm/i915/i915_reg.h

609

#define EU_PERF_CNTL2 _MMIO(0xe658)

sys/dev/drm/i915/i915_reg.h

6094

#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \

sys/dev/drm/i915/i915_reg.h

610

#define EU_PERF_CNTL3 _MMIO(0xe758)

sys/dev/drm/i915/i915_reg.h

611

#define EU_PERF_CNTL4 _MMIO(0xe45c)

sys/dev/drm/i915/i915_reg.h

612

#define EU_PERF_CNTL5 _MMIO(0xe55c)

sys/dev/drm/i915/i915_reg.h

613

#define EU_PERF_CNTL6 _MMIO(0xe65c)

sys/dev/drm/i915/i915_reg.h

619

#define OASTARTTRIG1 _MMIO(0x2710)

sys/dev/drm/i915/i915_reg.h

6201

#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

6202

#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

6203

#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

6204

#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

623

#define OASTARTTRIG2 _MMIO(0x2714)

sys/dev/drm/i915/i915_reg.h

6461

_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))

sys/dev/drm/i915/i915_reg.h

654

#define OASTARTTRIG3 _MMIO(0x2718)

sys/dev/drm/i915/i915_reg.h

665

#define OASTARTTRIG4 _MMIO(0x271c)

sys/dev/drm/i915/i915_reg.h

6720

#define VGACNTRL _MMIO(0x71400)

sys/dev/drm/i915/i915_reg.h

6725

#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)

sys/dev/drm/i915/i915_reg.h

6729

#define CPU_VGACNTRL _MMIO(0x41000)

sys/dev/drm/i915/i915_reg.h

6731

#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)

sys/dev/drm/i915/i915_reg.h

6744

#define RR_HW_CTL _MMIO(0x45300)

sys/dev/drm/i915/i915_reg.h

6748

#define FDI_PLL_BIOS_0 _MMIO(0x46000)

sys/dev/drm/i915/i915_reg.h

6750

#define FDI_PLL_BIOS_1 _MMIO(0x46004)

sys/dev/drm/i915/i915_reg.h

6751

#define FDI_PLL_BIOS_2 _MMIO(0x46008)

sys/dev/drm/i915/i915_reg.h

6752

#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)

sys/dev/drm/i915/i915_reg.h

6753

#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)

sys/dev/drm/i915/i915_reg.h

6754

#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)

sys/dev/drm/i915/i915_reg.h

6756

#define PCH_3DCGDIS0 _MMIO(0x46020)

sys/dev/drm/i915/i915_reg.h

676

#define OASTARTTRIG5 _MMIO(0x2720)

sys/dev/drm/i915/i915_reg.h

6760

#define PCH_3DCGDIS1 _MMIO(0x46024)

sys/dev/drm/i915/i915_reg.h

6763

#define FDI_PLL_FREQ_CTL _MMIO(0x46030)

sys/dev/drm/i915/i915_reg.h

680

#define OASTARTTRIG6 _MMIO(0x2724)

sys/dev/drm/i915/i915_reg.h

6972

#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)

sys/dev/drm/i915/i915_reg.h

6984

#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

6987

#define CSR_SSP_BASE _MMIO(0x8F074)

sys/dev/drm/i915/i915_reg.h

6988

#define CSR_HTP_SKL _MMIO(0x8F004)

sys/dev/drm/i915/i915_reg.h

6989

#define CSR_LAST_WRITE _MMIO(0x8F034)

sys/dev/drm/i915/i915_reg.h

6994

#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)

sys/dev/drm/i915/i915_reg.h

6995

#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)

sys/dev/drm/i915/i915_reg.h

6996

#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)

sys/dev/drm/i915/i915_reg.h

7050

#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */

sys/dev/drm/i915/i915_reg.h

7053

#define DEISR _MMIO(0x44000)

sys/dev/drm/i915/i915_reg.h

7054

#define DEIMR _MMIO(0x44004)

sys/dev/drm/i915/i915_reg.h

7055

#define DEIIR _MMIO(0x44008)

sys/dev/drm/i915/i915_reg.h

7056

#define DEIER _MMIO(0x4400c)

sys/dev/drm/i915/i915_reg.h

7058

#define GTISR _MMIO(0x44010)

sys/dev/drm/i915/i915_reg.h

7059

#define GTIMR _MMIO(0x44014)

sys/dev/drm/i915/i915_reg.h

7060

#define GTIIR _MMIO(0x44018)

sys/dev/drm/i915/i915_reg.h

7061

#define GTIER _MMIO(0x4401c)

sys/dev/drm/i915/i915_reg.h

7063

#define GEN8_MASTER_IRQ _MMIO(0x44200)

sys/dev/drm/i915/i915_reg.h

7081

#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))

sys/dev/drm/i915/i915_reg.h

7082

#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))

sys/dev/drm/i915/i915_reg.h

7083

#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))

sys/dev/drm/i915/i915_reg.h

7084

#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))

sys/dev/drm/i915/i915_reg.h

7103

#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7104

#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7105

#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7106

#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

711

#define OASTARTTRIG7 _MMIO(0x2728)

sys/dev/drm/i915/i915_reg.h

7139

#define GEN8_DE_PORT_ISR _MMIO(0x44440)

sys/dev/drm/i915/i915_reg.h

7140

#define GEN8_DE_PORT_IMR _MMIO(0x44444)

sys/dev/drm/i915/i915_reg.h

7141

#define GEN8_DE_PORT_IIR _MMIO(0x44448)

sys/dev/drm/i915/i915_reg.h

7142

#define GEN8_DE_PORT_IER _MMIO(0x4444c)

sys/dev/drm/i915/i915_reg.h

7158

#define GEN8_DE_MISC_ISR _MMIO(0x44460)

sys/dev/drm/i915/i915_reg.h

7159

#define GEN8_DE_MISC_IMR _MMIO(0x44464)

sys/dev/drm/i915/i915_reg.h

7160

#define GEN8_DE_MISC_IIR _MMIO(0x44468)

sys/dev/drm/i915/i915_reg.h

7161

#define GEN8_DE_MISC_IER _MMIO(0x4446c)

sys/dev/drm/i915/i915_reg.h

7165

#define GEN8_PCU_ISR _MMIO(0x444e0)

sys/dev/drm/i915/i915_reg.h

7166

#define GEN8_PCU_IMR _MMIO(0x444e4)

sys/dev/drm/i915/i915_reg.h

7167

#define GEN8_PCU_IIR _MMIO(0x444e8)

sys/dev/drm/i915/i915_reg.h

7168

#define GEN8_PCU_IER _MMIO(0x444ec)

sys/dev/drm/i915/i915_reg.h

7170

#define GEN11_GU_MISC_ISR _MMIO(0x444f0)

sys/dev/drm/i915/i915_reg.h

7171

#define GEN11_GU_MISC_IMR _MMIO(0x444f4)

sys/dev/drm/i915/i915_reg.h

7172

#define GEN11_GU_MISC_IIR _MMIO(0x444f8)

sys/dev/drm/i915/i915_reg.h

7173

#define GEN11_GU_MISC_IER _MMIO(0x444fc)

sys/dev/drm/i915/i915_reg.h

7176

#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)

sys/dev/drm/i915/i915_reg.h

7185

#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)

sys/dev/drm/i915/i915_reg.h

7196

#define GEN11_DE_HPD_ISR _MMIO(0x44470)

sys/dev/drm/i915/i915_reg.h

7197

#define GEN11_DE_HPD_IMR _MMIO(0x44474)

sys/dev/drm/i915/i915_reg.h

7198

#define GEN11_DE_HPD_IIR _MMIO(0x44478)

sys/dev/drm/i915/i915_reg.h

7199

#define GEN11_DE_HPD_IER _MMIO(0x4447c)

sys/dev/drm/i915/i915_reg.h

7219

#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)

sys/dev/drm/i915/i915_reg.h

722

#define OASTARTTRIG8 _MMIO(0x272c)

sys/dev/drm/i915/i915_reg.h

7220

#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)

sys/dev/drm/i915/i915_reg.h

7226

#define GEN11_GT_INTR_DW0 _MMIO(0x190018)

sys/dev/drm/i915/i915_reg.h

7236

#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)

sys/dev/drm/i915/i915_reg.h

7240

#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))

sys/dev/drm/i915/i915_reg.h

7242

#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)

sys/dev/drm/i915/i915_reg.h

7243

#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)

sys/dev/drm/i915/i915_reg.h

7249

#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))

sys/dev/drm/i915/i915_reg.h

7251

#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)

sys/dev/drm/i915/i915_reg.h

7252

#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)

sys/dev/drm/i915/i915_reg.h

7254

#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))

sys/dev/drm/i915/i915_reg.h

7256

#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)

sys/dev/drm/i915/i915_reg.h

7257

#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)

sys/dev/drm/i915/i915_reg.h

7258

#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)

sys/dev/drm/i915/i915_reg.h

7259

#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)

sys/dev/drm/i915/i915_reg.h

7260

#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)

sys/dev/drm/i915/i915_reg.h

7261

#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)

sys/dev/drm/i915/i915_reg.h

7263

#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)

sys/dev/drm/i915/i915_reg.h

7264

#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)

sys/dev/drm/i915/i915_reg.h

7265

#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)

sys/dev/drm/i915/i915_reg.h

7266

#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)

sys/dev/drm/i915/i915_reg.h

7267

#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)

sys/dev/drm/i915/i915_reg.h

7268

#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)

sys/dev/drm/i915/i915_reg.h

7269

#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)

sys/dev/drm/i915/i915_reg.h

7270

#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)

sys/dev/drm/i915/i915_reg.h

7271

#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)

sys/dev/drm/i915/i915_reg.h

7273

#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)

sys/dev/drm/i915/i915_reg.h

7278

#define FUSE_STRAP _MMIO(0x42014)

sys/dev/drm/i915/i915_reg.h

7288

#define ILK_DSPCLK_GATE_D _MMIO(0x42020)

sys/dev/drm/i915/i915_reg.h

7295

#define IVB_CHICKEN3 _MMIO(0x4200c)

sys/dev/drm/i915/i915_reg.h

7299

#define CHICKEN_PAR1_1 _MMIO(0x42080)

sys/dev/drm/i915/i915_reg.h

7305

#define CHICKEN_PAR2_1 _MMIO(0x42090)

sys/dev/drm/i915/i915_reg.h

7308

#define CHICKEN_MISC_2 _MMIO(0x42084)

sys/dev/drm/i915/i915_reg.h

7314

#define CHICKEN_MISC_4 _MMIO(0x4208c)

sys/dev/drm/i915/i915_reg.h

733

#define OAREPORTTRIG1 _MMIO(0x2740)

sys/dev/drm/i915/i915_reg.h

7335

#define DISP_ARB_CTL _MMIO(0x45000)

sys/dev/drm/i915/i915_reg.h

7339

#define DISP_ARB_CTL2 _MMIO(0x45004)

sys/dev/drm/i915/i915_reg.h

7342

#define DBUF_CTL _MMIO(0x45008)

sys/dev/drm/i915/i915_reg.h

7343

#define DBUF_CTL_S1 _MMIO(0x45008)

sys/dev/drm/i915/i915_reg.h

7344

#define DBUF_CTL_S2 _MMIO(0x44FE8)

sys/dev/drm/i915/i915_reg.h

7347

#define GEN7_MSG_CTL _MMIO(0x45010)

sys/dev/drm/i915/i915_reg.h

7350

#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)

sys/dev/drm/i915/i915_reg.h

7353

#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)

sys/dev/drm/i915/i915_reg.h

7358

#define SKL_DFSM _MMIO(0x51000)

sys/dev/drm/i915/i915_reg.h

7368

#define SKL_DSSM _MMIO(0x51004)

sys/dev/drm/i915/i915_reg.h

737

#define OAREPORTTRIG2 _MMIO(0x2744)

sys/dev/drm/i915/i915_reg.h

7375

#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)

sys/dev/drm/i915/i915_reg.h

7378

#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)

sys/dev/drm/i915/i915_reg.h

7382

#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)

sys/dev/drm/i915/i915_reg.h

7383

#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)

sys/dev/drm/i915/i915_reg.h

7384

#define GEN8_CS_CHICKEN1 _MMIO(0x2580)

sys/dev/drm/i915/i915_reg.h

7393

#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)

sys/dev/drm/i915/i915_reg.h

7397

#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)

sys/dev/drm/i915/i915_reg.h

7403

#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)

sys/dev/drm/i915/i915_reg.h

7406

#define HIZ_CHICKEN _MMIO(0x7018)

sys/dev/drm/i915/i915_reg.h

7410

#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)

sys/dev/drm/i915/i915_reg.h

7413

#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)

sys/dev/drm/i915/i915_reg.h

7416

#define GEN7_L3SQCREG1 _MMIO(0xB010)

sys/dev/drm/i915/i915_reg.h

7419

#define GEN8_L3SQCREG1 _MMIO(0xB100)

sys/dev/drm/i915/i915_reg.h

7430

#define GEN7_L3CNTLREG1 _MMIO(0xB01C)

sys/dev/drm/i915/i915_reg.h

7433

#define GEN7_L3CNTLREG2 _MMIO(0xB020)

sys/dev/drm/i915/i915_reg.h

7434

#define GEN7_L3CNTLREG3 _MMIO(0xB024)

sys/dev/drm/i915/i915_reg.h

7436

#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)

sys/dev/drm/i915/i915_reg.h

7438

#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)

sys/dev/drm/i915/i915_reg.h

7441

#define GEN7_L3SQCREG4 _MMIO(0xb034)

sys/dev/drm/i915/i915_reg.h

7444

#define GEN8_L3SQCREG4 _MMIO(0xb118)

sys/dev/drm/i915/i915_reg.h

7450

#define HDC_CHICKEN0 _MMIO(0x7300)

sys/dev/drm/i915/i915_reg.h

7451

#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)

sys/dev/drm/i915/i915_reg.h

7452

#define ICL_HDC_MODE _MMIO(0xE5F4)

sys/dev/drm/i915/i915_reg.h

7460

#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)

sys/dev/drm/i915/i915_reg.h

7463

#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)

sys/dev/drm/i915/i915_reg.h

7466

#define GEN9_WM_CHICKEN3 _MMIO(0x5588)

sys/dev/drm/i915/i915_reg.h

7470

#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)

sys/dev/drm/i915/i915_reg.h

7473

#define HSW_SCRATCH1 _MMIO(0xb038)

sys/dev/drm/i915/i915_reg.h

7476

#define BDW_SCRATCH1 _MMIO(0xb11c)

sys/dev/drm/i915/i915_reg.h

7597

#define SDEISR _MMIO(0xc4000)

sys/dev/drm/i915/i915_reg.h

7598

#define SDEIMR _MMIO(0xc4004)

sys/dev/drm/i915/i915_reg.h

7599

#define SDEIIR _MMIO(0xc4008)

sys/dev/drm/i915/i915_reg.h

7600

#define SDEIER _MMIO(0xc400c)

sys/dev/drm/i915/i915_reg.h

7602

#define SERR_INT _MMIO(0xc4040)

sys/dev/drm/i915/i915_reg.h

7607

#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */

sys/dev/drm/i915/i915_reg.h

764

#define OAREPORTTRIG3 _MMIO(0x2748)

sys/dev/drm/i915/i915_reg.h

7650

#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */

sys/dev/drm/i915/i915_reg.h

7662

#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)

sys/dev/drm/i915/i915_reg.h

7676

#define SHOTPLUG_CTL_TC _MMIO(0xc4034)

sys/dev/drm/i915/i915_reg.h

7679

#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)

sys/dev/drm/i915/i915_reg.h

7680

#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)

sys/dev/drm/i915/i915_reg.h

7681

#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)

sys/dev/drm/i915/i915_reg.h

7682

#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)

sys/dev/drm/i915/i915_reg.h

7707

#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)

sys/dev/drm/i915/i915_reg.h

7708

#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)

sys/dev/drm/i915/i915_reg.h

7709

#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)

sys/dev/drm/i915/i915_reg.h

7710

#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)

sys/dev/drm/i915/i915_reg.h

7732

#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)

sys/dev/drm/i915/i915_reg.h

7733

#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)

sys/dev/drm/i915/i915_reg.h

7734

#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)

sys/dev/drm/i915/i915_reg.h

7735

#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)

sys/dev/drm/i915/i915_reg.h

775

#define OAREPORTTRIG4 _MMIO(0x274c)

sys/dev/drm/i915/i915_reg.h

7757

#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)

sys/dev/drm/i915/i915_reg.h

7758

#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)

sys/dev/drm/i915/i915_reg.h

7759

#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)

sys/dev/drm/i915/i915_reg.h

7760

#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)

sys/dev/drm/i915/i915_reg.h

7787

#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)

sys/dev/drm/i915/i915_reg.h

7794

#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)

sys/dev/drm/i915/i915_reg.h

7795

#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)

sys/dev/drm/i915/i915_reg.h

7797

#define PCH_DPLL_TEST _MMIO(0xc606c)

sys/dev/drm/i915/i915_reg.h

7799

#define PCH_DREF_CONTROL _MMIO(0xC6200)

sys/dev/drm/i915/i915_reg.h

7822

#define PCH_RAWCLK_FREQ _MMIO(0xc6204)

sys/dev/drm/i915/i915_reg.h

7835

#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)

sys/dev/drm/i915/i915_reg.h

7837

#define PCH_SSC4_PARMS _MMIO(0xc6210)

sys/dev/drm/i915/i915_reg.h

7838

#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)

sys/dev/drm/i915/i915_reg.h

7840

#define PCH_DPLL_SEL _MMIO(0xc7000)

sys/dev/drm/i915/i915_reg.h

786

#define OAREPORTTRIG5 _MMIO(0x2750)

sys/dev/drm/i915/i915_reg.h

790

#define OAREPORTTRIG6 _MMIO(0x2754)

sys/dev/drm/i915/i915_reg.h

8039

#define SOUTH_CHICKEN1 _MMIO(0xc2000)

sys/dev/drm/i915/i915_reg.h

8048

#define SOUTH_CHICKEN2 _MMIO(0xc2004)

sys/dev/drm/i915/i915_reg.h

8060

#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)

sys/dev/drm/i915/i915_reg.h

817

#define OAREPORTTRIG7 _MMIO(0x2758)

sys/dev/drm/i915/i915_reg.h

8186

#define FDI_PLL_CTL_1 _MMIO(0xfe000)

sys/dev/drm/i915/i915_reg.h

8187

#define FDI_PLL_CTL_2 _MMIO(0xfe004)

sys/dev/drm/i915/i915_reg.h

8189

#define PCH_LVDS _MMIO(0xe1180)

sys/dev/drm/i915/i915_reg.h

8193

#define PCH_DP_B _MMIO(_PCH_DP_B)

sys/dev/drm/i915/i915_reg.h

8202

#define PCH_DP_C _MMIO(_PCH_DP_C)

sys/dev/drm/i915/i915_reg.h

8211

#define PCH_DP_D _MMIO(_PCH_DP_D)

sys/dev/drm/i915/i915_reg.h

8220

#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */

sys/dev/drm/i915/i915_reg.h

8276

#define VLV_PMWGICZ _MMIO(0x1300a4)

sys/dev/drm/i915/i915_reg.h

8278

#define RC6_LOCATION _MMIO(0xD40)

sys/dev/drm/i915/i915_reg.h

828

#define OAREPORTTRIG8 _MMIO(0x275c)

sys/dev/drm/i915/i915_reg.h

8280

#define RC6_CTX_BASE _MMIO(0xD48)

sys/dev/drm/i915/i915_reg.h

8282

#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)

sys/dev/drm/i915/i915_reg.h

8283

#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)

sys/dev/drm/i915/i915_reg.h

8284

#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)

sys/dev/drm/i915/i915_reg.h

8285

#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)

sys/dev/drm/i915/i915_reg.h

8286

#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)

sys/dev/drm/i915/i915_reg.h

8288

#define FORCEWAKE _MMIO(0xA18C)

sys/dev/drm/i915/i915_reg.h

8289

#define FORCEWAKE_VLV _MMIO(0x1300b0)

sys/dev/drm/i915/i915_reg.h

8290

#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)

sys/dev/drm/i915/i915_reg.h

8291

#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)

sys/dev/drm/i915/i915_reg.h

8292

#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)

sys/dev/drm/i915/i915_reg.h

8293

#define FORCEWAKE_ACK_HSW _MMIO(0x130044)

sys/dev/drm/i915/i915_reg.h

8294

#define FORCEWAKE_ACK _MMIO(0x130090)

sys/dev/drm/i915/i915_reg.h

8295

#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)

sys/dev/drm/i915/i915_reg.h

8300

#define VLV_GTLC_PW_STATUS _MMIO(0x130094)

sys/dev/drm/i915/i915_reg.h

8305

#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */

sys/dev/drm/i915/i915_reg.h

8306

#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)

sys/dev/drm/i915/i915_reg.h

8307

#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)

sys/dev/drm/i915/i915_reg.h

8308

#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)

sys/dev/drm/i915/i915_reg.h

8309

#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)

sys/dev/drm/i915/i915_reg.h

8310

#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)

sys/dev/drm/i915/i915_reg.h

8311

#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)

sys/dev/drm/i915/i915_reg.h

8312

#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)

sys/dev/drm/i915/i915_reg.h

8313

#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)

sys/dev/drm/i915/i915_reg.h

8314

#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)

sys/dev/drm/i915/i915_reg.h

8315

#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)

sys/dev/drm/i915/i915_reg.h

8319

#define FORCEWAKE_MT_ACK _MMIO(0x130040)

sys/dev/drm/i915/i915_reg.h

8320

#define ECOBUS _MMIO(0xa180)

sys/dev/drm/i915/i915_reg.h

8322

#define VLV_SPAREG2H _MMIO(0xA194)

sys/dev/drm/i915/i915_reg.h

8323

#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)

sys/dev/drm/i915/i915_reg.h

8327

#define GTFIFODBG _MMIO(0x120000)

sys/dev/drm/i915/i915_reg.h

8338

#define GTFIFOCTL _MMIO(0x120008)

sys/dev/drm/i915/i915_reg.h

8344

#define HSW_IDICR _MMIO(0x9008)

sys/dev/drm/i915/i915_reg.h

8346

#define HSW_EDRAM_CAP _MMIO(0x120010)

sys/dev/drm/i915/i915_reg.h

8352

#define GEN6_UCGCTL1 _MMIO(0x9400)

sys/dev/drm/i915/i915_reg.h

8358

#define GEN6_UCGCTL2 _MMIO(0x9404)

sys/dev/drm/i915/i915_reg.h

8366

#define GEN6_UCGCTL3 _MMIO(0x9408)

sys/dev/drm/i915/i915_reg.h

8369

#define GEN7_UCGCTL4 _MMIO(0x940c)

sys/dev/drm/i915/i915_reg.h

8373

#define GEN6_RCGCTL1 _MMIO(0x9410)

sys/dev/drm/i915/i915_reg.h

8374

#define GEN6_RCGCTL2 _MMIO(0x9414)

sys/dev/drm/i915/i915_reg.h

8375

#define GEN6_RSTCTL _MMIO(0x9420)

sys/dev/drm/i915/i915_reg.h

8377

#define GEN8_UCGCTL6 _MMIO(0x9430)

sys/dev/drm/i915/i915_reg.h

8382

#define GEN6_GFXPAUSE _MMIO(0xA000)

sys/dev/drm/i915/i915_reg.h

8383

#define GEN6_RPNSWREQ _MMIO(0xA008)

sys/dev/drm/i915/i915_reg.h

8390

#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)

sys/dev/drm/i915/i915_reg.h

8391

#define GEN6_RC_CONTROL _MMIO(0xA090)

sys/dev/drm/i915/i915_reg.h

8401

#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)

sys/dev/drm/i915/i915_reg.h

8402

#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)

sys/dev/drm/i915/i915_reg.h

8403

#define GEN6_RPSTAT1 _MMIO(0xA01C)

sys/dev/drm/i915/i915_reg.h

8410

#define GEN6_RP_CONTROL _MMIO(0xA024)

sys/dev/drm/i915/i915_reg.h

8424

#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)

sys/dev/drm/i915/i915_reg.h

8425

#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)

sys/dev/drm/i915/i915_reg.h

8426

#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)

sys/dev/drm/i915/i915_reg.h

8429

#define GEN6_RP_CUR_UP _MMIO(0xA054)

sys/dev/drm/i915/i915_reg.h

8431

#define GEN6_RP_PREV_UP _MMIO(0xA058)

sys/dev/drm/i915/i915_reg.h

8432

#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)

sys/dev/drm/i915/i915_reg.h

8434

#define GEN6_RP_CUR_DOWN _MMIO(0xA060)

sys/dev/drm/i915/i915_reg.h

8435

#define GEN6_RP_PREV_DOWN _MMIO(0xA064)

sys/dev/drm/i915/i915_reg.h

8436

#define GEN6_RP_UP_EI _MMIO(0xA068)

sys/dev/drm/i915/i915_reg.h

8437

#define GEN6_RP_DOWN_EI _MMIO(0xA06C)

sys/dev/drm/i915/i915_reg.h

8438

#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)

sys/dev/drm/i915/i915_reg.h

8439

#define GEN6_RPDEUHWTC _MMIO(0xA080)

sys/dev/drm/i915/i915_reg.h

8440

#define GEN6_RPDEUC _MMIO(0xA084)

sys/dev/drm/i915/i915_reg.h

8441

#define GEN6_RPDEUCSW _MMIO(0xA088)

sys/dev/drm/i915/i915_reg.h

8442

#define GEN6_RC_STATE _MMIO(0xA094)

sys/dev/drm/i915/i915_reg.h

8445

#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)

sys/dev/drm/i915/i915_reg.h

8446

#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)

sys/dev/drm/i915/i915_reg.h

8447

#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)

sys/dev/drm/i915/i915_reg.h

8448

#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)

sys/dev/drm/i915/i915_reg.h

8449

#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)

sys/dev/drm/i915/i915_reg.h

8450

#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)

sys/dev/drm/i915/i915_reg.h

8451

#define GEN6_RC_SLEEP _MMIO(0xA0B0)

sys/dev/drm/i915/i915_reg.h

8452

#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)

sys/dev/drm/i915/i915_reg.h

8453

#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)

sys/dev/drm/i915/i915_reg.h

8454

#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)

sys/dev/drm/i915/i915_reg.h

8455

#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)

sys/dev/drm/i915/i915_reg.h

8456

#define VLV_RCEDATA _MMIO(0xA0BC)

sys/dev/drm/i915/i915_reg.h

8457

#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)

sys/dev/drm/i915/i915_reg.h

8458

#define GEN6_PMINTRMSK _MMIO(0xA168)

sys/dev/drm/i915/i915_reg.h

8461

#define GEN8_MISC_CTRL0 _MMIO(0xA180)

sys/dev/drm/i915/i915_reg.h

8462

#define VLV_PWRDWNUPCTL _MMIO(0xA294)

sys/dev/drm/i915/i915_reg.h

8463

#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)

sys/dev/drm/i915/i915_reg.h

8464

#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)

sys/dev/drm/i915/i915_reg.h

8465

#define GEN9_PG_ENABLE _MMIO(0xA210)

sys/dev/drm/i915/i915_reg.h

8468

#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)

sys/dev/drm/i915/i915_reg.h

8469

#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)

sys/dev/drm/i915/i915_reg.h

8470

#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)

sys/dev/drm/i915/i915_reg.h

8472

#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)

sys/dev/drm/i915/i915_reg.h

8476

#define GEN6_PMISR _MMIO(0x44020)

sys/dev/drm/i915/i915_reg.h

8477

#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */

sys/dev/drm/i915/i915_reg.h

8478

#define GEN6_PMIIR _MMIO(0x44028)

sys/dev/drm/i915/i915_reg.h

8479

#define GEN6_PMIER _MMIO(0x4402C)

sys/dev/drm/i915/i915_reg.h

8493

#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

8496

#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)

sys/dev/drm/i915/i915_reg.h

8500

#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)

sys/dev/drm/i915/i915_reg.h

8501

#define VLV_COUNTER_CONTROL _MMIO(0x138104)

sys/dev/drm/i915/i915_reg.h

8507

#define GEN6_GT_GFX_RC6 _MMIO(0x138108)

sys/dev/drm/i915/i915_reg.h

8508

#define VLV_GT_RENDER_RC6 _MMIO(0x138108)

sys/dev/drm/i915/i915_reg.h

8509

#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)

sys/dev/drm/i915/i915_reg.h

8511

#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)

sys/dev/drm/i915/i915_reg.h

8512

#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)

sys/dev/drm/i915/i915_reg.h

8513

#define VLV_RENDER_C0_COUNT _MMIO(0x138118)

sys/dev/drm/i915/i915_reg.h

8514

#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)

sys/dev/drm/i915/i915_reg.h

8516

#define GEN6_PCODE_MAILBOX _MMIO(0x138124)

sys/dev/drm/i915/i915_reg.h

8555

#define GEN6_PCODE_DATA _MMIO(0x138128)

sys/dev/drm/i915/i915_reg.h

8558

#define GEN6_PCODE_DATA1 _MMIO(0x13812C)

sys/dev/drm/i915/i915_reg.h

8560

#define GEN6_GT_CORE_STATUS _MMIO(0x138060)

sys/dev/drm/i915/i915_reg.h

8568

#define GEN8_GT_SLICE_INFO _MMIO(0x138064)

sys/dev/drm/i915/i915_reg.h

8571

#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)

sys/dev/drm/i915/i915_reg.h

8572

#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)

sys/dev/drm/i915/i915_reg.h

8578

#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)

sys/dev/drm/i915/i915_reg.h

8579

#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)

sys/dev/drm/i915/i915_reg.h

8582

#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)

sys/dev/drm/i915/i915_reg.h

8583

#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \

sys/dev/drm/i915/i915_reg.h

8589

#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)

sys/dev/drm/i915/i915_reg.h

8590

#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \

sys/dev/drm/i915/i915_reg.h

8592

#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)

sys/dev/drm/i915/i915_reg.h

8593

#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \

sys/dev/drm/i915/i915_reg.h

860

#define OACEC0_0 _MMIO(0x2770)

sys/dev/drm/i915/i915_reg.h

8604

#define GEN7_MISCCPCTL _MMIO(0x9424)

sys/dev/drm/i915/i915_reg.h

861

#define OACEC0_1 _MMIO(0x2774)

sys/dev/drm/i915/i915_reg.h

8610

#define GEN8_GARBCNTL _MMIO(0xB004)

sys/dev/drm/i915/i915_reg.h

8616

#define GEN11_GLBLINVL _MMIO(0xB404)

sys/dev/drm/i915/i915_reg.h

862

#define OACEC1_0 _MMIO(0x2778)

sys/dev/drm/i915/i915_reg.h

8620

#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)

sys/dev/drm/i915/i915_reg.h

8623

#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)

sys/dev/drm/i915/i915_reg.h

8628

#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)

sys/dev/drm/i915/i915_reg.h

863

#define OACEC1_1 _MMIO(0x277c)

sys/dev/drm/i915/i915_reg.h

8632

#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)

sys/dev/drm/i915/i915_reg.h

8636

#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */

sys/dev/drm/i915/i915_reg.h

864

#define OACEC2_0 _MMIO(0x2780)

sys/dev/drm/i915/i915_reg.h

8649

#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)

sys/dev/drm/i915/i915_reg.h

865

#define OACEC2_1 _MMIO(0x2784)

sys/dev/drm/i915/i915_reg.h

8652

#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */

sys/dev/drm/i915/i915_reg.h

8653

#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)

sys/dev/drm/i915/i915_reg.h

8659

#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)

sys/dev/drm/i915/i915_reg.h

866

#define OACEC3_0 _MMIO(0x2788)

sys/dev/drm/i915/i915_reg.h

8663

#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)

sys/dev/drm/i915/i915_reg.h

867

#define OACEC3_1 _MMIO(0x278c)

sys/dev/drm/i915/i915_reg.h

8670

#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)

sys/dev/drm/i915/i915_reg.h

8671

#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)

sys/dev/drm/i915/i915_reg.h

8676

#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)

sys/dev/drm/i915/i915_reg.h

8679

#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)

sys/dev/drm/i915/i915_reg.h

868

#define OACEC4_0 _MMIO(0x2790)

sys/dev/drm/i915/i915_reg.h

8682

#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)

sys/dev/drm/i915/i915_reg.h

8689

#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)

sys/dev/drm/i915/i915_reg.h

869

#define OACEC4_1 _MMIO(0x2794)

sys/dev/drm/i915/i915_reg.h

8695

#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)

sys/dev/drm/i915/i915_reg.h

870

#define OACEC5_0 _MMIO(0x2798)

sys/dev/drm/i915/i915_reg.h

8700

#define G4X_AUD_CNTL_ST _MMIO(0x620B4)

sys/dev/drm/i915/i915_reg.h

8705

#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)

sys/dev/drm/i915/i915_reg.h

871

#define OACEC5_1 _MMIO(0x279c)

sys/dev/drm/i915/i915_reg.h

8718

#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)

sys/dev/drm/i915/i915_reg.h

872

#define OACEC6_0 _MMIO(0x27a0)

sys/dev/drm/i915/i915_reg.h

8728

#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)

sys/dev/drm/i915/i915_reg.h

873

#define OACEC6_1 _MMIO(0x27a4)

sys/dev/drm/i915/i915_reg.h

8736

#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)

sys/dev/drm/i915/i915_reg.h

874

#define OACEC7_0 _MMIO(0x27a8)

sys/dev/drm/i915/i915_reg.h

8742

#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)

sys/dev/drm/i915/i915_reg.h

875

#define OACEC7_1 _MMIO(0x27ac)

sys/dev/drm/i915/i915_reg.h

878

#define OA_PERFCNT1_LO _MMIO(0x91B8)

sys/dev/drm/i915/i915_reg.h

879

#define OA_PERFCNT1_HI _MMIO(0x91BC)

sys/dev/drm/i915/i915_reg.h

880

#define OA_PERFCNT2_LO _MMIO(0x91C0)

sys/dev/drm/i915/i915_reg.h

8808

#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)

sys/dev/drm/i915/i915_reg.h

8809

#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)

sys/dev/drm/i915/i915_reg.h

881

#define OA_PERFCNT2_HI _MMIO(0x91C4)

sys/dev/drm/i915/i915_reg.h

8815

#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)

sys/dev/drm/i915/i915_reg.h

882

#define OA_PERFCNT3_LO _MMIO(0x91C8)

sys/dev/drm/i915/i915_reg.h

883

#define OA_PERFCNT3_HI _MMIO(0x91CC)

sys/dev/drm/i915/i915_reg.h

8833

#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)

sys/dev/drm/i915/i915_reg.h

8834

#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)

sys/dev/drm/i915/i915_reg.h

8835

#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)

sys/dev/drm/i915/i915_reg.h

8836

#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)

sys/dev/drm/i915/i915_reg.h

884

#define OA_PERFCNT4_LO _MMIO(0x91D8)

sys/dev/drm/i915/i915_reg.h

885

#define OA_PERFCNT4_HI _MMIO(0x91DC)

sys/dev/drm/i915/i915_reg.h

8865

#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)

sys/dev/drm/i915/i915_reg.h

8866

#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)

sys/dev/drm/i915/i915_reg.h

8867

#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)

sys/dev/drm/i915/i915_reg.h

887

#define OA_PERFMATRIX_LO _MMIO(0x91C8)

sys/dev/drm/i915/i915_reg.h

8879

#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)

sys/dev/drm/i915/i915_reg.h

888

#define OA_PERFMATRIX_HI _MMIO(0x91CC)

sys/dev/drm/i915/i915_reg.h

8880

#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)

sys/dev/drm/i915/i915_reg.h

8881

#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)

sys/dev/drm/i915/i915_reg.h

8890

#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)

sys/dev/drm/i915/i915_reg.h

8894

#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)

sys/dev/drm/i915/i915_reg.h

8905

#define SKL_FUSE_STATUS _MMIO(0x42000)

sys/dev/drm/i915/i915_reg.h

891

#define RPM_CONFIG0 _MMIO(0x0D00)

sys/dev/drm/i915/i915_reg.h

8926

#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \

sys/dev/drm/i915/i915_reg.h

8935

#define HDCP_KEY_CONF _MMIO(0x66c00)

sys/dev/drm/i915/i915_reg.h

8939

#define HDCP_KEY_STATUS _MMIO(0x66c04)

sys/dev/drm/i915/i915_reg.h

8945

#define HDCP_AKSV_LO _MMIO(0x66c10)

sys/dev/drm/i915/i915_reg.h

8946

#define HDCP_AKSV_HI _MMIO(0x66c14)

sys/dev/drm/i915/i915_reg.h

8949

#define HDCP_REP_CTL _MMIO(0x66d00)

sys/dev/drm/i915/i915_reg.h

8972

#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)

sys/dev/drm/i915/i915_reg.h

8973

#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)

sys/dev/drm/i915/i915_reg.h

8974

#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)

sys/dev/drm/i915/i915_reg.h

8975

#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)

sys/dev/drm/i915/i915_reg.h

8976

#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)

sys/dev/drm/i915/i915_reg.h

8977

#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))

sys/dev/drm/i915/i915_reg.h

8978

#define HDCP_SHA_TEXT _MMIO(0x66d18)

sys/dev/drm/i915/i915_reg.h

8987

#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \

sys/dev/drm/i915/i915_reg.h

905

#define RPM_CONFIG1 _MMIO(0x0D04)

sys/dev/drm/i915/i915_reg.h

909

#define CTC_MODE _MMIO(0xA26C)

sys/dev/drm/i915/i915_reg.h

9107

#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)

sys/dev/drm/i915/i915_reg.h

9109

#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)

sys/dev/drm/i915/i915_reg.h

9114

#define SBI_ADDR _MMIO(0xC6000)

sys/dev/drm/i915/i915_reg.h

9115

#define SBI_DATA _MMIO(0xC6004)

sys/dev/drm/i915/i915_reg.h

9116

#define SBI_CTL_STAT _MMIO(0xC6008)

sys/dev/drm/i915/i915_reg.h

9153

#define PIXCLK_GATE _MMIO(0xC6020)

sys/dev/drm/i915/i915_reg.h

9158

#define SPLL_CTL _MMIO(0x46020)

sys/dev/drm/i915/i915_reg.h

917

#define RCP_CONFIG _MMIO(0x0D08)

sys/dev/drm/i915/i915_reg.h

920

#define HSW_MBVID2_NOA0 _MMIO(0x9E80)

sys/dev/drm/i915/i915_reg.h

921

#define HSW_MBVID2_NOA1 _MMIO(0x9E84)

sys/dev/drm/i915/i915_reg.h

922

#define HSW_MBVID2_NOA2 _MMIO(0x9E88)

sys/dev/drm/i915/i915_reg.h

9220

#define CDCLK_FREQ _MMIO(0x46200)

sys/dev/drm/i915/i915_reg.h

923

#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)

sys/dev/drm/i915/i915_reg.h

9237

#define LCPLL_CTL _MMIO(0x130040)

sys/dev/drm/i915/i915_reg.h

924

#define HSW_MBVID2_NOA4 _MMIO(0x9E90)

sys/dev/drm/i915/i915_reg.h

925

#define HSW_MBVID2_NOA5 _MMIO(0x9E94)

sys/dev/drm/i915/i915_reg.h

9257

#define CDCLK_CTL _MMIO(0x46000)

sys/dev/drm/i915/i915_reg.h

926

#define HSW_MBVID2_NOA6 _MMIO(0x9E98)

sys/dev/drm/i915/i915_reg.h

927

#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)

sys/dev/drm/i915/i915_reg.h

9276

#define LCPLL1_CTL _MMIO(0x46010)

sys/dev/drm/i915/i915_reg.h

9277

#define LCPLL2_CTL _MMIO(0x46014)

sys/dev/drm/i915/i915_reg.h

928

#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)

sys/dev/drm/i915/i915_reg.h

9281

#define DPLL_CTRL1 _MMIO(0x6C058)

sys/dev/drm/i915/i915_reg.h

929

#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)

sys/dev/drm/i915/i915_reg.h

9296

#define DPLL_CTRL2 _MMIO(0x6C05C)

sys/dev/drm/i915/i915_reg.h

9304

#define DPLL_STATUS _MMIO(0x6C060)

sys/dev/drm/i915/i915_reg.h

931

#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)

sys/dev/drm/i915/i915_reg.h

934

#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)

sys/dev/drm/i915/i915_reg.h

9342

#define DPCLKA_CFGCR0 _MMIO(0x6C200)

sys/dev/drm/i915/i915_reg.h

9343

#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)

sys/dev/drm/i915/i915_reg.h

936

#define MICRO_BP0_0 _MMIO(0x9800)

sys/dev/drm/i915/i915_reg.h

9363

#define TBT_PLL_ENABLE _MMIO(0x46020)

sys/dev/drm/i915/i915_reg.h

937

#define MICRO_BP0_2 _MMIO(0x9804)

sys/dev/drm/i915/i915_reg.h

938

#define MICRO_BP0_1 _MMIO(0x9808)

sys/dev/drm/i915/i915_reg.h

940

#define MICRO_BP1_0 _MMIO(0x980C)

sys/dev/drm/i915/i915_reg.h

941

#define MICRO_BP1_2 _MMIO(0x9810)

sys/dev/drm/i915/i915_reg.h

942

#define MICRO_BP1_1 _MMIO(0x9814)

sys/dev/drm/i915/i915_reg.h

944

#define MICRO_BP2_0 _MMIO(0x9818)

sys/dev/drm/i915/i915_reg.h

945

#define MICRO_BP2_2 _MMIO(0x981C)

sys/dev/drm/i915/i915_reg.h

946

#define MICRO_BP2_1 _MMIO(0x9820)

sys/dev/drm/i915/i915_reg.h

948

#define MICRO_BP3_0 _MMIO(0x9824)

sys/dev/drm/i915/i915_reg.h

949

#define MICRO_BP3_2 _MMIO(0x9828)

sys/dev/drm/i915/i915_reg.h

950

#define MICRO_BP3_1 _MMIO(0x982C)

sys/dev/drm/i915/i915_reg.h

952

#define MICRO_BP_TRIGGER _MMIO(0x9830)

sys/dev/drm/i915/i915_reg.h

953

#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)

sys/dev/drm/i915/i915_reg.h

954

#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)

sys/dev/drm/i915/i915_reg.h

955

#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)

sys/dev/drm/i915/i915_reg.h

957

#define GDT_CHICKEN_BITS _MMIO(0x9840)

sys/dev/drm/i915/i915_reg.h

9571

#define BXT_DE_PLL_CTL _MMIO(0x6d000)

sys/dev/drm/i915/i915_reg.h

9575

#define BXT_DE_PLL_ENABLE _MMIO(0x46070)

sys/dev/drm/i915/i915_reg.h

9582

#define DC_STATE_EN _MMIO(0x45504)

sys/dev/drm/i915/i915_reg.h

9589

#define DC_STATE_DEBUG _MMIO(0x45520)

sys/dev/drm/i915/i915_reg.h

9593

#define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)

sys/dev/drm/i915/i915_reg.h

960

#define NOA_DATA _MMIO(0x986C)

sys/dev/drm/i915/i915_reg.h

9603

#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \

sys/dev/drm/i915/i915_reg.h

961

#define NOA_WRITE _MMIO(0x9888)

sys/dev/drm/i915/i915_reg.h

9624

#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)

sys/dev/drm/i915/i915_reg.h

9627

#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)

sys/dev/drm/i915/i915_reg.h

9628

#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)

sys/dev/drm/i915/i915_reg.h

9643

#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)

sys/dev/drm/i915/i915_reg.h

9644

#define D_COMP_BDW _MMIO(0x138144)

sys/dev/drm/i915/i915_reg.h

9659

#define SFUSE_STRAP _MMIO(0xc2014)

sys/dev/drm/i915/i915_reg.h

9669

#define WM_MISC _MMIO(0x45260)

sys/dev/drm/i915/i915_reg.h

9672

#define WM_DBG _MMIO(0x45280)

sys/dev/drm/i915/i915_reg.h

970

#define DEBUG_RESET_I830 _MMIO(0x6070)

sys/dev/drm/i915/i915_reg.h

9746

#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)

sys/dev/drm/i915/i915_reg.h

9747

#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)

sys/dev/drm/i915/i915_reg.h

978

#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)

sys/dev/drm/i915/i915_reg.h

9787

#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)

sys/dev/drm/i915/i915_reg.h

9788

#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)

sys/dev/drm/i915/i915_reg.h

9794

#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))

sys/dev/drm/i915/i915_reg.h

9796

#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)

sys/dev/drm/i915/i915_reg.h

9798

#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)

sys/dev/drm/i915/i915_reg.h

9818

#define GEN4_TIMESTAMP _MMIO(0x2358)

sys/dev/drm/i915/i915_reg.h

9819

#define ILK_TIMESTAMP_HI _MMIO(0x70070)

sys/dev/drm/i915/i915_reg.h

9820

#define IVB_TIMESTAMP_CTR _MMIO(0x44070)

sys/dev/drm/i915/i915_reg.h

9822

#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)

sys/dev/drm/i915/i915_reg.h

9835

#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)

sys/dev/drm/i915/i915_reg.h

9914

#define BXT_DSI_PLL_CTL _MMIO(0x161000)

sys/dev/drm/i915/i915_reg.h

9938

#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)

sys/dev/drm/i915/i915_reg.h

9959

#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)

sys/dev/drm/i915/i915_reg.h

9962

#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)

sys/dev/drm/i915/intel_csr.c

399

csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);

sys/dev/drm/i915/intel_guc.c

47

return _MMIO(guc->send_regs.base + 4 * i);

sys/dev/drm/i915/intel_guc_reg.h

104

#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)

sys/dev/drm/i915/intel_guc_reg.h

107

#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)

sys/dev/drm/i915/intel_guc_reg.h

109

#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)

sys/dev/drm/i915/intel_guc_reg.h

111

#define DE_GUCRMR _MMIO(0x44054)

sys/dev/drm/i915/intel_guc_reg.h

113

#define GUC_BCS_RCS_IER _MMIO(0xC550)

sys/dev/drm/i915/intel_guc_reg.h

114

#define GUC_VCS2_VCS1_IER _MMIO(0xC554)

sys/dev/drm/i915/intel_guc_reg.h

115

#define GUC_WD_VECS_IER _MMIO(0xC558)

sys/dev/drm/i915/intel_guc_reg.h

116

#define GUC_PM_P24C_IER _MMIO(0xC55C)

sys/dev/drm/i915/intel_guc_reg.h

29

#define GUC_STATUS _MMIO(0xc000)

sys/dev/drm/i915/intel_guc_reg.h

51

#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)

sys/dev/drm/i915/intel_guc_reg.h

54

#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)

sys/dev/drm/i915/intel_guc_reg.h

57

#define DMA_ADDR_0_LOW _MMIO(0xc300)

sys/dev/drm/i915/intel_guc_reg.h

58

#define DMA_ADDR_0_HIGH _MMIO(0xc304)

sys/dev/drm/i915/intel_guc_reg.h

59

#define DMA_ADDR_1_LOW _MMIO(0xc308)

sys/dev/drm/i915/intel_guc_reg.h

60

#define DMA_ADDR_1_HIGH _MMIO(0xc30c)

sys/dev/drm/i915/intel_guc_reg.h

63

#define DMA_COPY_SIZE _MMIO(0xc310)

sys/dev/drm/i915/intel_guc_reg.h

64

#define DMA_CTRL _MMIO(0xc314)

sys/dev/drm/i915/intel_guc_reg.h

68

#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)

sys/dev/drm/i915/intel_guc_reg.h

74

#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)

sys/dev/drm/i915/intel_guc_reg.h

76

#define HUC_STATUS2 _MMIO(0xD3B0)

sys/dev/drm/i915/intel_guc_reg.h

79

#define GUC_WOPCM_SIZE _MMIO(0xc050)

sys/dev/drm/i915/intel_guc_reg.h

84

#define GEN8_GT_PM_CONFIG _MMIO(0x138140)

sys/dev/drm/i915/intel_guc_reg.h

85

#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)

sys/dev/drm/i915/intel_guc_reg.h

86

#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)

sys/dev/drm/i915/intel_guc_reg.h

89

#define GEN8_GTCR _MMIO(0x4274)

sys/dev/drm/i915/intel_guc_reg.h

92

#define GUC_ARAT_C6DIS _MMIO(0xA178)

sys/dev/drm/i915/intel_guc_reg.h

94

#define GUC_SHIM_CONTROL _MMIO(0xc064)

sys/dev/drm/i915/intel_lrc.h

31

#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)

sys/dev/drm/i915/intel_lrc.h

32

#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)

sys/dev/drm/i915/intel_lrc.h

33

#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)

sys/dev/drm/i915/intel_lrc.h

34

#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)

sys/dev/drm/i915/intel_lrc.h

39

#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)

sys/dev/drm/i915/intel_lrc.h

40

#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)

sys/dev/drm/i915/intel_lrc.h

41

#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)

sys/dev/drm/i915/intel_lrc.h

42

#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)

sys/dev/drm/i915/intel_lrc.h

43

#define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)

sys/dev/drm/i915/intel_lrc.h

44

#define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550)