sys/dev/drm/i915/i915_gem.c

5634

I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));

sys/dev/drm/i915/i915_gem.c

5636

I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));

sys/dev/drm/i915/i915_gem.c

5638

I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));

sys/dev/drm/i915/i915_gem_gtt.c

1797

_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));

sys/dev/drm/i915/i915_gem_gtt.c

1822

_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

sys/dev/drm/i915/i915_gem_gtt.c

1840

I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

sys/dev/drm/i915/i915_perf.c

1803

_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |

sys/dev/drm/i915/i915_perf.c

3043

val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);

sys/dev/drm/i915/i915_perf.c

3050

val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);

sys/dev/drm/i915/intel_engine_cs.c

727

I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));

sys/dev/drm/i915/intel_guc_fw.c

180

I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));

sys/dev/drm/i915/intel_guc_submission.c

1059

_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \

sys/dev/drm/i915/intel_guc_submission.c

1181

irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);

sys/dev/drm/i915/intel_huc_fw.c

136

I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));

sys/dev/drm/i915/intel_lrc.c

1788

_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));

sys/dev/drm/i915/intel_lrc.c

1847

I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

sys/dev/drm/i915/intel_lrc.c

1849

I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

sys/dev/drm/i915/intel_lrc.c

2678

_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));

sys/dev/drm/i915/intel_lrc.c

2805

_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);

sys/dev/drm/i915/intel_lrc.c

2808

_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |

sys/dev/drm/i915/intel_pm.c

373

val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :

sys/dev/drm/i915/intel_pm.c

384

val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :

sys/dev/drm/i915/intel_pm.c

7615

_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |

sys/dev/drm/i915/intel_pm.c

7704

_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |

sys/dev/drm/i915/intel_pm.c

8561

_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));

sys/dev/drm/i915/intel_pm.c

8629

_MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));

sys/dev/drm/i915/intel_pm.c

8672

_MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));

sys/dev/drm/i915/intel_pm.c

8680

_MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));

sys/dev/drm/i915/intel_pm.c

8806

_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));

sys/dev/drm/i915/intel_pm.c

8906

_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));

sys/dev/drm/i915/intel_pm.c

8938

_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));

sys/dev/drm/i915/intel_pm.c

8958

_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

sys/dev/drm/i915/intel_pm.c

8973

_MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));

sys/dev/drm/i915/intel_pm.c

8989

_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));

sys/dev/drm/i915/intel_pm.c

8999

_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));

sys/dev/drm/i915/intel_pm.c

9015

_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

sys/dev/drm/i915/intel_pm.c

9019

_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

sys/dev/drm/i915/intel_pm.c

9021

_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

sys/dev/drm/i915/intel_pm.c

9052

_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

sys/dev/drm/i915/intel_pm.c

9080

_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));

sys/dev/drm/i915/intel_pm.c

9090

_MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |

sys/dev/drm/i915/intel_pm.c

9102

_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

sys/dev/drm/i915/intel_pm.c

9129

_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

sys/dev/drm/i915/intel_pm.c

9166

_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));

sys/dev/drm/i915/intel_pm.c

9208

_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));

sys/dev/drm/i915/intel_pm.c

9224

_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

sys/dev/drm/i915/intel_pm.c

9239

_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

sys/dev/drm/i915/intel_pm.c

9254

I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));

sys/dev/drm/i915/intel_pm.c

9260

I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));

sys/dev/drm/i915/intel_pm.c

9263

I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));

sys/dev/drm/i915/intel_pm.c

9266

_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

sys/dev/drm/i915/intel_pm.c

9274

I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |

sys/dev/drm/i915/intel_pm.c

9278

_MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));

sys/dev/drm/i915/intel_pm.c

9284

_MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |

sys/dev/drm/i915/intel_pm.c

9285

_MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));

sys/dev/drm/i915/intel_pm.c

9754

_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));

sys/dev/drm/i915/intel_pm.c

9764

_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));

sys/dev/drm/i915/intel_ringbuffer.c

1605

*cs++ = _MASKED_BIT_ENABLE(

sys/dev/drm/i915/intel_ringbuffer.c

1993

_MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));

sys/dev/drm/i915/intel_ringbuffer.c

455

_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |

sys/dev/drm/i915/intel_ringbuffer.c

470

I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));

sys/dev/drm/i915/intel_ringbuffer.c

669

I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));

sys/dev/drm/i915/intel_ringbuffer.c

678

I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

sys/dev/drm/i915/intel_ringbuffer.c

684

_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));

sys/dev/drm/i915/intel_ringbuffer.c

689

_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |

sys/dev/drm/i915/intel_ringbuffer.c

690

_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));

sys/dev/drm/i915/intel_ringbuffer.c

703

I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

sys/dev/drm/i915/intel_uncore.c

1408

dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);

sys/dev/drm/i915/intel_uncore.c

152

_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK));

sys/dev/drm/i915/intel_uncore.c

2094

_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));

sys/dev/drm/i915/intel_workarounds.c

119

WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))

sys/dev/drm/i915/intel_workarounds.c

629

.val = _MASKED_BIT_ENABLE(val)