_MASKED_BIT_DISABLE
_MASKED_BIT_DISABLE(STOP_RING));
irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
_MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
_MASKED_BIT_DISABLE(STOP_RING));
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
_MASKED_BIT_DISABLE(INSTPM_SELF_EN);
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
_MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
_MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
*cs++ = _MASKED_BIT_DISABLE(
_MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff);
dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL_FALLBACK));
_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))