sys/dev/drm/i915/intel_ddi.c

1677

link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));

sys/dev/drm/i915/intel_ddi.c

1680

link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));

sys/dev/drm/i915/intel_display.c

9148

I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");

sys/dev/drm/i915/intel_display.c

9149

I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");

sys/dev/drm/i915/intel_dpll_mgr.c

480

I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);

sys/dev/drm/i915/intel_dpll_mgr.c

481

POSTING_READ(WRPLL_CTL(id));

sys/dev/drm/i915/intel_dpll_mgr.c

499

val = I915_READ(WRPLL_CTL(id));

sys/dev/drm/i915/intel_dpll_mgr.c

500

I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);

sys/dev/drm/i915/intel_dpll_mgr.c

501

POSTING_READ(WRPLL_CTL(id));

sys/dev/drm/i915/intel_dpll_mgr.c

524

val = I915_READ(WRPLL_CTL(id));

sys/dev/drm/i915/intel_dpll_mgr.c

915

.ctl = WRPLL_CTL(0),

sys/dev/drm/i915/intel_dpll_mgr.c

921

.ctl = WRPLL_CTL(1),