sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

235

WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

236

WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

237

WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

238

WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

240

WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

250

WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

252

WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

292

WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

254

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

255

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

256

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

257

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

259

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

269

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

271

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

324

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);