Symbol: WREG32_SOC15_DPG_MODE
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1004
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1006
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1009
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1015
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1021
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1028
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1029
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1032
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1035
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1040
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1045
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1057
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1058
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1061
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
356
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
359
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
362
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
366
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
368
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
371
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
375
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
378
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
380
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
382
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
384
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
388
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
391
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
394
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
395
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
399
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
401
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
403
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
405
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
407
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
409
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
411
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
413
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
415
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
417
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
632
WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
634
WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
663
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
666
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
669
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
672
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
983
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
986
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
990
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,