sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

243

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

250

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

251

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

252

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

253

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

254

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

257

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

258

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

259

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

260

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

261

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

264

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

273

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

299

WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

303

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

310

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

311

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

314

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

316

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

318

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

319

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

320

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

324

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

333

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/drm/amd/amdgpu/df_v1_7.c

44

WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);

sys/dev/drm/amd/amdgpu/df_v1_7.c

46

WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,

sys/dev/drm/amd/amdgpu/df_v1_7.c

82

WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);

sys/dev/drm/amd/amdgpu/df_v1_7.c

87

WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);

sys/dev/drm/amd/amdgpu/df_v3_6.c

45

WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);

sys/dev/drm/amd/amdgpu/df_v3_6.c

47

WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,

sys/dev/drm/amd/amdgpu/df_v3_6.c

85

WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);

sys/dev/drm/amd/amdgpu/df_v3_6.c

90

WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1008

WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1019

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1020

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1021

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1022

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1025

WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1028

WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1033

WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1039

WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1045

WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1057

WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1310

WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1322

WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1602

WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1608

WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1613

WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1617

WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1621

WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1625

WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1629

WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1633

WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1886

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1954

WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1955

WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1983

WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1984

WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1988

WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1993

WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2009

WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2070

WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2175

WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2179

WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2180

WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2184

WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2460

WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2464

WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2485

WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2488

WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2489

WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2506

WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2544

WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2577

WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2579

WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2580

WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2587

WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2589

WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2590

WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2597

WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2599

WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2600

WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2613

WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2614

WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2675

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2678

WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2688

WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2692

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2693

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2697

WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2698

WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2701

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2702

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2705

WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2708

WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2709

WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2720

WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2724

WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2726

WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2742

WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2744

WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2774

WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2776

WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2778

WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2782

WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2785

WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2788

WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2805

WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2807

WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3027

WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3029

WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3033

WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3037

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3042

WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3048

WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3050

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3052

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3054

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3059

WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3061

WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3065

WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3069

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3071

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3075

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3079

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3081

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3085

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3087

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3092

WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3094

WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3098

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3102

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3104

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3108

WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3110

WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3114

WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3131

WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3143

WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3146

WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3150

WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3151

WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3152

WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3153

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3154

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3155

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3156

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3157

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3525

WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3531

WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3546

WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3630

WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3661

WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3723

WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3732

WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3739

WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3755

WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3761

WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3768

WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3788

WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3799

WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3806

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3815

WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3838

WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3849

WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3856

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3863

WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4042

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4043

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4278

WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4279

WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4959

WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

947

WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

957

WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

970

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

971

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

972

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

973

WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

976

WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

979

WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

984

WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

990

WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

996

WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

100

WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

102

WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

127

WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

144

WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

149

WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

161

WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

166

WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

176

WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

181

WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

183

WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

186

WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

188

WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

191

WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

192

WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

265

WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

267

WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

301

WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

305

WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

349

WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

42

WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

45

WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

53

WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

55

WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

58

WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

60

WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

69

WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

70

WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

71

WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

74

WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

84

WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

88

WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

94

WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

96

WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1124

WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

102

WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

106

WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

112

WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

114

WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

118

WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

120

WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

126

WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

147

WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

164

WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

169

WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

184

WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

194

WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

199

WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

201

WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

204

WREG32_SOC15(MMHUB, 0,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

206

WREG32_SOC15(MMHUB, 0,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

209

WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

211

WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

297

WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

299

WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

333

WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

338

WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

339

WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

383

WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

459

WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

463

WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

465

WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

469

WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

485

WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

501

WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

518

WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

59

WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

62

WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

70

WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

72

WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

75

WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

77

WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

87

WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

88

WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

89

WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

92

WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

107

WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

109

WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

113

WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

128

WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

136

WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

144

WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

49

WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

53

WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

111

WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

118

WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

127

WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

128

WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

211

WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

219

WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

50

WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

53

WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

102

WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

104

WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

108

WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

122

WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

173

WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

181

WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

48

WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

51

WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

215

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

218

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

221

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

225

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

249

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

322

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

171

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,

sys/dev/drm/amd/amdgpu/psp_v11_0.c

174

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,

sys/dev/drm/amd/amdgpu/psp_v11_0.c

212

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,

sys/dev/drm/amd/amdgpu/psp_v11_0.c

215

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,

sys/dev/drm/amd/amdgpu/psp_v11_0.c

283

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

286

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

289

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

293

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

312

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

387

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

198

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,

sys/dev/drm/amd/amdgpu/psp_v3_1.c

201

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,

sys/dev/drm/amd/amdgpu/psp_v3_1.c

258

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,

sys/dev/drm/amd/amdgpu/psp_v3_1.c

261

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,

sys/dev/drm/amd/amdgpu/psp_v3_1.c

333

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

336

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

339

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

343

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

367

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

442

WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

575

WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg);

sys/dev/drm/amd/amdgpu/soc15.c

170

WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

181

WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

182

WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));

sys/dev/drm/amd/amdgpu/soc15.c

192

WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

203

WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

204

WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));

sys/dev/drm/amd/amdgpu/soc15_common.h

74

({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \

sys/dev/drm/amd/amdgpu/soc15_common.h

75

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \

sys/dev/drm/amd/amdgpu/soc15_common.h

84

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \

sys/dev/drm/amd/amdgpu/soc15_common.h

85

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \

sys/dev/drm/amd/amdgpu/soc15_common.h

86

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1001

WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1002

WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1004

WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1005

WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1006

WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1007

WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1008

WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1009

WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1012

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1017

WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1025

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1073

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1076

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1079

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1083

WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1085

WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1089

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1092

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1099

WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1100

WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1101

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1102

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1103

WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1106

WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1107

WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1108

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1109

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1110

WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1130

WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1139

WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1144

WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1236

WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

140

WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

162

WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1637

WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1638

WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1639

WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1640

WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

165

WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1680

WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1681

WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1740

WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

669

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

673

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

677

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

680

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

682

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

685

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

689

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

691

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

693

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

695

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

696

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

698

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

700

WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

702

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

703

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

706

WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

708

WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

710

WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

713

WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

729

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

730

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

736

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

739

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

742

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

753

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

976

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

988

WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1071

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1074

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1077

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1081

WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1083

WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1087

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1089

WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1092

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1161

WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1282

WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1285

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1488

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1491

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1608

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

289

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

291

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

293

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

296

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

298

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

301

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

305

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

308

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

310

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

312

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

313

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

316

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

318

WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

320

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

321

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

323

WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

325

WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

327

WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

329

WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

331

WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

333

WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

335

WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

337

WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

339

WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

341

WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

343

WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

345

WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

443

WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

447

WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

458

WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

481

WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

504

WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

532

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

545

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

568

WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

572

WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

582

WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

605

WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

618

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

693

WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

707

WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

718

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

731

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

746

WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

783

WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

794

WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

804

WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

809

WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

811

WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

817

WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

823

WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

830

WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

831

WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

835

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

848

WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

889

WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

898

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

901

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

904

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

908

WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

910

WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

914

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

916

WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

919

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

926

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

927

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

928

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

929

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

930

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

933

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

934

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

935

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

936

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

937

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

940

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

941

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

943

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

944

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

945

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

946

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

947

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

974

WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);

sys/dev/drm/amd/amdgpu/vega10_ih.c

103

WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);

sys/dev/drm/amd/amdgpu/vega10_ih.c

104

WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);

sys/dev/drm/amd/amdgpu/vega10_ih.c

107

WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/vega10_ih.c

108

WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff);

sys/dev/drm/amd/amdgpu/vega10_ih.c

124

WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/vega10_ih.c

131

WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/vega10_ih.c

132

WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);

sys/dev/drm/amd/amdgpu/vega10_ih.c

135

WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

136

WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

148

WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);

sys/dev/drm/amd/amdgpu/vega10_ih.c

155

WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);

sys/dev/drm/amd/amdgpu/vega10_ih.c

159

WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);

sys/dev/drm/amd/amdgpu/vega10_ih.c

372

WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);

sys/dev/drm/amd/amdgpu/vega10_ih.c

51

WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/vega10_ih.c

68

WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/vega10_ih.c

70

WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

71

WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1000

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1009

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1061

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1072

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1111

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1120

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1170

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

949

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

964

WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

142

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

145

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

162

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

166

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

278

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

326

WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

392

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

407

WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

413

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

447

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

474

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);

sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c

196

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);

sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c

215

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);

sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c

228

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

160

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

203

WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

266

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

285

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

298

WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

94

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

97

WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

102

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

104

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

66

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

84

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

108

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

136

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

138

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

44

WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

89

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

112

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

138

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

140

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

52

WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

94

WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);