sys/dev/drm/radeon/radeon_legacy_crtc.c

1014

WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,

sys/dev/drm/radeon/radeon_legacy_crtc.c

231

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/drm/radeon/radeon_legacy_crtc.c

258

WREG32_PLL_P(RADEON_P2PLL_REF_DIV,

sys/dev/drm/radeon/radeon_legacy_crtc.c

861

WREG32_PLL_P(RADEON_PIXCLKS_CNTL,

sys/dev/drm/radeon/radeon_legacy_crtc.c

865

WREG32_PLL_P(RADEON_P2PLL_CNTL,

sys/dev/drm/radeon/radeon_legacy_crtc.c

873

WREG32_PLL_P(RADEON_P2PLL_REF_DIV,

sys/dev/drm/radeon/radeon_legacy_crtc.c

877

WREG32_PLL_P(RADEON_P2PLL_DIV_0,

sys/dev/drm/radeon/radeon_legacy_crtc.c

881

WREG32_PLL_P(RADEON_P2PLL_DIV_0,

sys/dev/drm/radeon/radeon_legacy_crtc.c

890

WREG32_PLL_P(RADEON_P2PLL_CNTL,

sys/dev/drm/radeon/radeon_legacy_crtc.c

909

WREG32_PLL_P(RADEON_PIXCLKS_CNTL,

sys/dev/drm/radeon/radeon_legacy_crtc.c

942

WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,

sys/dev/drm/radeon/radeon_legacy_crtc.c

945

WREG32_PLL_P(RADEON_PPLL_CNTL,

sys/dev/drm/radeon/radeon_legacy_crtc.c

968

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/drm/radeon/radeon_legacy_crtc.c

973

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/drm/radeon/radeon_legacy_crtc.c

978

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/drm/radeon/radeon_legacy_crtc.c

982

WREG32_PLL_P(RADEON_PPLL_DIV_3,

sys/dev/drm/radeon/radeon_legacy_crtc.c

986

WREG32_PLL_P(RADEON_PPLL_DIV_3,

sys/dev/drm/radeon/radeon_legacy_crtc.c

995

WREG32_PLL_P(RADEON_PPLL_CNTL,

sys/dev/drm/radeon/radeon_legacy_encoders.c

109

WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);

sys/dev/drm/radeon/radeon_legacy_tv.c

770

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);

sys/dev/drm/radeon/radeon_legacy_tv.c

772

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);

sys/dev/drm/radeon/radeon_legacy_tv.c

776

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);

sys/dev/drm/radeon/radeon_legacy_tv.c

781

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);

sys/dev/drm/radeon/radeon_legacy_tv.c

782

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);

sys/dev/drm/radeon/radeon_legacy_tv.c

784

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);

sys/dev/drm/radeon/radeon_legacy_tv.c

785

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);