sys/dev/drm/amd/amdgpu/amdgpu.h

1136

WREG32_PLL(reg, tmp_); \

sys/dev/drm/radeon/r100.c

2702

WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);

sys/dev/drm/radeon/r100.c

3897

WREG32_PLL(R_00000D_SCLK_CNTL, tmp);

sys/dev/drm/radeon/r100.c

420

WREG32_PLL(SCLK_CNTL, sclk_cntl);

sys/dev/drm/radeon/r100.c

421

WREG32_PLL(SCLK_CNTL2, sclk_cntl2);

sys/dev/drm/radeon/r100.c

422

WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);

sys/dev/drm/radeon/r300.c

1365

WREG32_PLL(R_00000D_SCLK_CNTL, tmp);

sys/dev/drm/radeon/r420.c

201

WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);

sys/dev/drm/radeon/r520.c

87

WREG32_PLL(0x000D, tmp);

sys/dev/drm/radeon/radeon.h

2579

WREG32_PLL(reg, tmp_); \

sys/dev/drm/radeon/radeon_clocks.c

398

WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

402

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

408

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

414

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

421

WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);

sys/dev/drm/radeon/radeon_clocks.c

430

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

434

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

440

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

461

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

467

WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

492

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

515

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

520

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

525

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

541

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

550

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/drm/radeon/radeon_clocks.c

568

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

573

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

578

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

594

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

599

WREG32_PLL(RADEON_MCLK_MISC, tmp);

sys/dev/drm/radeon/radeon_clocks.c

631

WREG32_PLL(RADEON_MCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

636

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

643

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/drm/radeon/radeon_clocks.c

654

WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

659

WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

683

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

699

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

711

WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

725

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

732

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

746

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

758

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

762

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

768

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

785

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

791

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/drm/radeon/radeon_clocks.c

802

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

806

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

813

WREG32_PLL(RADEON_MCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

819

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

836

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

863

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

873

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/drm/radeon/radeon_clocks.c

881

WREG32_PLL(RADEON_MCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

890

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

903

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

909

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/drm/radeon/radeon_combios.c

2983

WREG32_PLL(reg, val);

sys/dev/drm/radeon/radeon_combios.c

3100

WREG32_PLL(addr, val);

sys/dev/drm/radeon/radeon_combios.c

3113

WREG32_PLL(addr, tmp);

sys/dev/drm/radeon/radeon_combios.c

3152

WREG32_PLL(RADEON_MCLK_CNTL,

sys/dev/drm/radeon/radeon_combios.c

3156

WREG32_PLL

sys/dev/drm/radeon/radeon_legacy_crtc.c

1019

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

888

WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

913

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

993

WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

121

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1602

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1676

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

667

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

710

WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

284

WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);

sys/dev/drm/radeon/radeon_legacy_tv.c

293

WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);

sys/dev/drm/radeon/radeon_legacy_tv.c

771

WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);

sys/dev/drm/radeon/rs600.c

262

WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);

sys/dev/drm/radeon/rs600.c

274

WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);

sys/dev/drm/radeon/rs600.c

281

WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);

sys/dev/drm/radeon/rs600.c

289

WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);

sys/dev/drm/radeon/rs600.c

296

WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);

sys/dev/drm/radeon/rv515.c

165

WREG32_PLL(0x000D, tmp);

sys/dev/drm/radeon/rv515.c

503

WREG32_PLL(R_00000F_CP_DYN_CNTL,

sys/dev/drm/radeon/rv515.c

505

WREG32_PLL(R_000011_E2_DYN_CNTL,

sys/dev/drm/radeon/rv515.c

507

WREG32_PLL(R_000013_IDCT_DYN_CNTL,