Symbol: WREG32_P
sys/dev/drm/amd/amdgpu/amdgpu.h
1129
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
sys/dev/drm/amd/amdgpu/amdgpu.h
1130
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
sys/dev/drm/amd/amdgpu/ci_dpm.c
1649
WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
sys/dev/drm/amd/amdgpu/ci_dpm.c
1696
WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
sys/dev/drm/amd/amdgpu/ci_dpm.c
232
WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
sys/dev/drm/amd/amdgpu/ci_dpm.c
238
WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
sys/dev/drm/amd/amdgpu/ci_dpm.c
247
WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
sys/dev/drm/amd/amdgpu/ci_smc.c
234
WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK,
sys/dev/drm/amd/amdgpu/ci_smc.c
245
WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
sys/dev/drm/amd/amdgpu/ci_smc.c
45
WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1637
WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1929
WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1295
WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1474
WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
260
WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
sys/dev/drm/amd/amdgpu/kv_smc.c
87
WREG32_P(mmSMC_IND_ACCESS_CNTL, 0,
sys/dev/drm/amd/amdgpu/si_dpm.c
3116
WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
3121
WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
3126
WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
3131
WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
3139
WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
3763
WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
3765
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/amd/amdgpu/si_dpm.c
3767
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/amd/amdgpu/si_dpm.c
3792
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/amd/amdgpu/si_dpm.c
3797
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/amd/amdgpu/si_dpm.c
3803
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
sys/dev/drm/amd/amdgpu/si_dpm.c
3805
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
sys/dev/drm/amd/amdgpu/si_dpm.c
4051
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/amd/amdgpu/si_dpm.c
4053
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/amd/amdgpu/si_dpm.c
4058
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
sys/dev/drm/amd/amdgpu/si_dpm.c
4140
WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
4141
WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
sys/dev/drm/amd/amdgpu/si_dpm.c
4197
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/amd/amdgpu/si_dpm.c
4199
WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
sys/dev/drm/amd/amdgpu/si_dpm.c
4200
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/amd/amdgpu/si_dpm.c
4230
WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
4242
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4244
WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4247
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
sys/dev/drm/amd/amdgpu/si_dpm.c
4250
WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
sys/dev/drm/amd/amdgpu/si_dpm.c
6165
WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
sys/dev/drm/amd/amdgpu/si_dpm.c
6167
WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
sys/dev/drm/amd/amdgpu/si_dpm.c
6430
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
6431
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
6432
WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
268
WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
274
WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
281
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
309
WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
311
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
313
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
315
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
332
WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
335
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
346
WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
348
WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
372
WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
414
WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
427
WREG32_P(0x3D49, 0, ~(1 << 2));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
429
WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
663
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
303
WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
312
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
315
WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
327
WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
357
WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
376
WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
379
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
389
WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
392
WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
423
WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
441
WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
452
WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
586
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
716
WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
811
WREG32_P(mmUVD_MASTINT_EN,
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
816
WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
880
WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
891
WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1021
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1042
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1046
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1057
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1062
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1095
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1133
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1147
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
947
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
962
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
966
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
970
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
sys/dev/drm/amd/amdgpu/vce_v2_0.c
130
WREG32_P(mmVCE_SOFT_RESET,
sys/dev/drm/amd/amdgpu/vce_v2_0.c
134
WREG32_P(mmVCE_SOFT_RESET, 0,
sys/dev/drm/amd/amdgpu/vce_v2_0.c
172
WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
sys/dev/drm/amd/amdgpu/vce_v2_0.c
173
WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
174
WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
178
WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
200
WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
236
WREG32_P(mmVCE_STATUS, 1, ~1);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
265
WREG32_P(mmVCE_STATUS, 0, ~1);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
291
WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
sys/dev/drm/amd/amdgpu/vce_v2_0.c
300
WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
303
WREG32_P(mmVCE_SOFT_RESET, 1, ~0x1);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
531
WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
307
WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
344
WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
534
WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
sys/dev/drm/amd/amdgpu/vce_v3_0.c
535
WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
536
WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
540
WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
577
WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
717
WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
1021
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
sys/dev/drm/amd/amdgpu/vce_v4_0.c
139
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
sys/dev/drm/amd/amdgpu/vce_v4_0.c
143
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
sys/dev/drm/amd/amdgpu/vce_v4_0.c
360
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,
sys/dev/drm/amd/amdgpu/vce_v4_0.c
363
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
365
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
sys/dev/drm/amd/amdgpu/vce_v4_0.c
372
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
385
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
388
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
sys/dev/drm/amd/amdgpu/vce_v4_0.c
393
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
606
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
607
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
608
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
612
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
652
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
653
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1095
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1140
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1149
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1153
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1157
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1188
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
789
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
838
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
842
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
864
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
868
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
879
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
883
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
922
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
sys/dev/drm/radeon/atombios_crtc.c
1399
WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
sys/dev/drm/radeon/atombios_crtc.c
1601
WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
sys/dev/drm/radeon/btc_dpm.c
1378
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/btc_dpm.c
1380
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/btc_dpm.c
1666
WREG32_P(SCLK_PSKIP_CNTL, PSKIP_ON_ALLOW_STOP_HI(32),
sys/dev/drm/radeon/btc_dpm.c
1773
WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
sys/dev/drm/radeon/btc_dpm.c
1777
WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
sys/dev/drm/radeon/btc_dpm.c
1818
WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
sys/dev/drm/radeon/btc_dpm.c
1821
WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
sys/dev/drm/radeon/ci_dpm.c
1531
WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
sys/dev/drm/radeon/ci_dpm.c
1577
WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
sys/dev/drm/radeon/ci_smc.c
230
WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
sys/dev/drm/radeon/ci_smc.c
240
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
sys/dev/drm/radeon/ci_smc.c
42
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
sys/dev/drm/radeon/cik.c
7927
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
sys/dev/drm/radeon/cypress_dpm.c
103
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/cypress_dpm.c
104
WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/cypress_dpm.c
105
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/cypress_dpm.c
110
WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
sys/dev/drm/radeon/cypress_dpm.c
1106
WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
sys/dev/drm/radeon/cypress_dpm.c
1107
WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
sys/dev/drm/radeon/cypress_dpm.c
1109
WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
sys/dev/drm/radeon/cypress_dpm.c
1110
WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
sys/dev/drm/radeon/cypress_dpm.c
141
WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
sys/dev/drm/radeon/cypress_dpm.c
143
WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/cypress_dpm.c
145
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/cypress_dpm.c
146
WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/cypress_dpm.c
147
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/cypress_dpm.c
151
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
sys/dev/drm/radeon/cypress_dpm.c
198
WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
199
WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
200
WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
201
WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
202
WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
203
WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
204
WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
205
WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
sys/dev/drm/radeon/cypress_dpm.c
227
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/cypress_dpm.c
230
WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
sys/dev/drm/radeon/cypress_dpm.c
232
WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
sys/dev/drm/radeon/cypress_dpm.c
233
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/cypress_dpm.c
234
WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
sys/dev/drm/radeon/cypress_dpm.c
235
WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);
sys/dev/drm/radeon/cypress_dpm.c
241
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/cypress_dpm.c
248
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/cypress_dpm.c
250
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/cypress_dpm.c
257
WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/cypress_dpm.c
259
WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/cypress_dpm.c
92
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/cypress_dpm.c
94
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/dce3_1_afmt.c
190
WREG32_P(HDMI0_ACR_32_0 + offset,
sys/dev/drm/radeon/dce3_1_afmt.c
193
WREG32_P(HDMI0_ACR_32_1 + offset,
sys/dev/drm/radeon/dce3_1_afmt.c
197
WREG32_P(HDMI0_ACR_44_0 + offset,
sys/dev/drm/radeon/dce3_1_afmt.c
200
WREG32_P(HDMI0_ACR_44_1 + offset,
sys/dev/drm/radeon/dce3_1_afmt.c
204
WREG32_P(HDMI0_ACR_48_0 + offset,
sys/dev/drm/radeon/dce3_1_afmt.c
207
WREG32_P(HDMI0_ACR_48_1 + offset,
sys/dev/drm/radeon/evergreen.c
1138
WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
sys/dev/drm/radeon/evergreen.c
1181
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/evergreen.c
1186
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
sys/dev/drm/radeon/evergreen.c
1190
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
sys/dev/drm/radeon/evergreen.c
1201
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
sys/dev/drm/radeon/evergreen.c
1204
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
sys/dev/drm/radeon/evergreen.c
1205
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
sys/dev/drm/radeon/evergreen.c
1208
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/evergreen.c
1217
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/evergreen.c
1220
WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
sys/dev/drm/radeon/evergreen.c
1223
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
sys/dev/drm/radeon/evergreen.c
1226
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
sys/dev/drm/radeon/evergreen.c
1229
WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
sys/dev/drm/radeon/evergreen.c
1231
WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
sys/dev/drm/radeon/evergreen.c
1234
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/evergreen.c
1242
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/evergreen.c
1247
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
sys/dev/drm/radeon/evergreen.c
1254
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/evergreen.c
4829
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
sys/dev/drm/radeon/evergreen_hdmi.c
237
WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
sys/dev/drm/radeon/kv_smc.c
84
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
sys/dev/drm/radeon/ni.c
1726
WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
sys/dev/drm/radeon/ni.c
1733
WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
sys/dev/drm/radeon/ni.c
2751
WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
sys/dev/drm/radeon/ni_dpm.c
1021
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/ni_dpm.c
1205
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/ni_dpm.c
1206
WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/ni_dpm.c
1207
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/ni_dpm.c
1211
WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
sys/dev/drm/radeon/ni_dpm.c
1541
WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
sys/dev/drm/radeon/ni_dpm.c
1546
WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
sys/dev/drm/radeon/ni_dpm.c
1551
WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
sys/dev/drm/radeon/ni_dpm.c
1556
WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
sys/dev/drm/radeon/ni_dpm.c
1564
WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
sys/dev/drm/radeon/ni_dpm.c
3503
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/ni_dpm.c
3505
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/r100.c
2756
WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
sys/dev/drm/radeon/r600.c
199
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/r600.c
204
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
sys/dev/drm/radeon/r600.c
208
WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
sys/dev/drm/radeon/r600.c
213
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
sys/dev/drm/radeon/r600.c
238
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/r600.c
242
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
sys/dev/drm/radeon/r600.c
246
WREG32_P(CG_UPLL_FUNC_CNTL,
sys/dev/drm/radeon/r600.c
250
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/r600.c
262
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/r600.c
267
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
sys/dev/drm/radeon/r600.c
270
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
sys/dev/drm/radeon/r600.c
277
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/r600_dpm.c
248
WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/r600_dpm.c
250
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/r600_dpm.c
270
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/r600_dpm.c
272
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/r600_dpm.c
278
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/r600_dpm.c
280
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/r600_dpm.c
285
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
sys/dev/drm/radeon/r600_dpm.c
291
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/r600_dpm.c
293
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/r600_dpm.c
307
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/r600_dpm.c
309
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/r600_dpm.c
315
WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/r600_dpm.c
317
WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/r600_dpm.c
323
WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);
sys/dev/drm/radeon/r600_dpm.c
325
WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);
sys/dev/drm/radeon/r600_dpm.c
362
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/r600_dpm.c
364
WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/r600_dpm.c
366
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
sys/dev/drm/radeon/r600_dpm.c
368
WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
sys/dev/drm/radeon/r600_dpm.c
378
WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);
sys/dev/drm/radeon/r600_dpm.c
383
WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK);
sys/dev/drm/radeon/r600_dpm.c
388
WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK);
sys/dev/drm/radeon/r600_dpm.c
393
WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK);
sys/dev/drm/radeon/r600_dpm.c
398
WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK);
sys/dev/drm/radeon/r600_dpm.c
403
WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK);
sys/dev/drm/radeon/r600_dpm.c
408
WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK);
sys/dev/drm/radeon/r600_dpm.c
413
WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK);
sys/dev/drm/radeon/r600_dpm.c
418
WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK);
sys/dev/drm/radeon/r600_dpm.c
423
WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK);
sys/dev/drm/radeon/r600_dpm.c
428
WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK);
sys/dev/drm/radeon/r600_dpm.c
433
WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK);
sys/dev/drm/radeon/r600_dpm.c
438
WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK);
sys/dev/drm/radeon/r600_dpm.c
443
WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK);
sys/dev/drm/radeon/r600_dpm.c
450
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
453
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
461
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
464
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
472
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
475
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
482
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
489
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
496
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
503
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
sys/dev/drm/radeon/r600_dpm.c
509
WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK);
sys/dev/drm/radeon/r600_dpm.c
514
WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK);
sys/dev/drm/radeon/r600_dpm.c
519
WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK);
sys/dev/drm/radeon/r600_dpm.c
568
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,
sys/dev/drm/radeon/r600_dpm.c
571
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,
sys/dev/drm/radeon/r600_dpm.c
580
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
sys/dev/drm/radeon/r600_dpm.c
589
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
sys/dev/drm/radeon/r600_dpm.c
598
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
sys/dev/drm/radeon/r600_dpm.c
611
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
sys/dev/drm/radeon/r600_dpm.c
622
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);
sys/dev/drm/radeon/r600_dpm.c
646
WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index),
sys/dev/drm/radeon/r600_dpm.c
755
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
sys/dev/drm/radeon/r600_dpm.c
756
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
sys/dev/drm/radeon/r600_dpm.c
757
WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
sys/dev/drm/radeon/r600_hdmi.c
188
WREG32_P(acr_ctl + offset,
sys/dev/drm/radeon/r600_hdmi.c
194
WREG32_P(HDMI0_ACR_32_0 + offset,
sys/dev/drm/radeon/r600_hdmi.c
197
WREG32_P(HDMI0_ACR_32_1 + offset,
sys/dev/drm/radeon/r600_hdmi.c
201
WREG32_P(HDMI0_ACR_44_0 + offset,
sys/dev/drm/radeon/r600_hdmi.c
204
WREG32_P(HDMI0_ACR_44_1 + offset,
sys/dev/drm/radeon/r600_hdmi.c
208
WREG32_P(HDMI0_ACR_48_0 + offset,
sys/dev/drm/radeon/r600_hdmi.c
211
WREG32_P(HDMI0_ACR_48_1 + offset,
sys/dev/drm/radeon/r600_hdmi.c
314
WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
sys/dev/drm/radeon/r600_hdmi.c
364
WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
sys/dev/drm/radeon/r600_hdmi.c
378
WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
sys/dev/drm/radeon/r600_hdmi.c
391
WREG32_P(HDMI0_60958_0 + offset,
sys/dev/drm/radeon/r600_hdmi.c
396
WREG32_P(HDMI0_60958_1 + offset,
sys/dev/drm/radeon/radeon.h
2572
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
sys/dev/drm/radeon/radeon.h
2573
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
sys/dev/drm/radeon/radeon_cursor.c
136
WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
sys/dev/drm/radeon/radeon_display.c
77
WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
sys/dev/drm/radeon/radeon_legacy_crtc.c
328
WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
sys/dev/drm/radeon/radeon_legacy_crtc.c
330
WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
sys/dev/drm/radeon/radeon_legacy_crtc.c
332
WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
sys/dev/drm/radeon/radeon_legacy_crtc.c
344
WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
sys/dev/drm/radeon/radeon_legacy_crtc.c
346
WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
sys/dev/drm/radeon/radeon_legacy_crtc.c
348
WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
sys/dev/drm/radeon/radeon_legacy_crtc.c
934
WREG32_P(RADEON_CLOCK_CNTL_INDEX,
sys/dev/drm/radeon/radeon_legacy_crtc.c
955
WREG32_P(RADEON_CLOCK_CNTL_INDEX,
sys/dev/drm/radeon/radeon_legacy_encoders.c
1285
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1322
WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1372
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1614
WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1670
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
sys/dev/drm/radeon/radeon_legacy_encoders.c
621
WREG32_P(RADEON_DAC_CNTL,
sys/dev/drm/radeon/radeon_uvd.c
1028
WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
sys/dev/drm/radeon/radeon_uvd.c
1033
WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
sys/dev/drm/radeon/radeon_uvd.c
1044
WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
sys/dev/drm/radeon/rs780_dpm.c
1063
WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
sys/dev/drm/radeon/rs780_dpm.c
201
WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
sys/dev/drm/radeon/rs780_dpm.c
204
WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
sys/dev/drm/radeon/rs780_dpm.c
213
WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
sys/dev/drm/radeon/rs780_dpm.c
216
WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
sys/dev/drm/radeon/rs780_dpm.c
219
WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
sys/dev/drm/radeon/rs780_dpm.c
260
WREG32_P(FVTHROT_PWM_CTRL_REG0,
sys/dev/drm/radeon/rs780_dpm.c
264
WREG32_P(FVTHROT_PWM_CTRL_REG0,
sys/dev/drm/radeon/rs780_dpm.c
268
WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
sys/dev/drm/radeon/rs780_dpm.c
272
WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
sys/dev/drm/radeon/rs780_dpm.c
274
WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
sys/dev/drm/radeon/rs780_dpm.c
287
WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
sys/dev/drm/radeon/rs780_dpm.c
306
WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
sys/dev/drm/radeon/rs780_dpm.c
309
WREG32_P(FVTHROT_CNTRL_REG, 0,
sys/dev/drm/radeon/rs780_dpm.c
316
WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
sys/dev/drm/radeon/rs780_dpm.c
318
WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
sys/dev/drm/radeon/rs780_dpm.c
338
WREG32_P(FVTHROT_FBDIV_REG2,
sys/dev/drm/radeon/rs780_dpm.c
342
WREG32_P(FVTHROT_CNTRL_REG,
sys/dev/drm/radeon/rs780_dpm.c
349
WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
sys/dev/drm/radeon/rs780_dpm.c
359
WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
sys/dev/drm/radeon/rs780_dpm.c
375
WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
sys/dev/drm/radeon/rs780_dpm.c
386
WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
sys/dev/drm/radeon/rs780_dpm.c
390
WREG32_P(FVTHROT_PWM_CTRL_REG0,
sys/dev/drm/radeon/rs780_dpm.c
394
WREG32_P(FVTHROT_PWM_CTRL_REG0,
sys/dev/drm/radeon/rs780_dpm.c
397
WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
sys/dev/drm/radeon/rs780_dpm.c
402
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
sys/dev/drm/radeon/rs780_dpm.c
412
WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
sys/dev/drm/radeon/rs780_dpm.c
414
WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
sys/dev/drm/radeon/rs780_dpm.c
416
WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
sys/dev/drm/radeon/rs780_dpm.c
418
WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
sys/dev/drm/radeon/rs780_dpm.c
422
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
sys/dev/drm/radeon/rs780_dpm.c
462
WREG32_P(FVTHROT_FBDIV_REG0,
sys/dev/drm/radeon/rs780_dpm.c
467
WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
sys/dev/drm/radeon/rs780_dpm.c
486
WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
sys/dev/drm/radeon/rs780_dpm.c
488
WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
sys/dev/drm/radeon/rs780_dpm.c
540
WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
sys/dev/drm/radeon/rs780_dpm.c
544
WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
sys/dev/drm/radeon/rs780_dpm.c
547
WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
sys/dev/drm/radeon/rs780_dpm.c
550
WREG32_P(FVTHROT_PWM_CTRL_REG0,
sys/dev/drm/radeon/rs780_dpm.c
554
WREG32_P(FVTHROT_PWM_CTRL_REG0,
sys/dev/drm/radeon/rs780_dpm.c
560
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
1174
WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,
sys/dev/drm/radeon/rv6xx_dpm.c
1177
WREG32_P(GENERAL_PWRMGT, 0,
sys/dev/drm/radeon/rv6xx_dpm.c
1213
WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
sys/dev/drm/radeon/rv6xx_dpm.c
1225
WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
sys/dev/drm/radeon/rv6xx_dpm.c
1238
WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
1240
WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
1259
WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
sys/dev/drm/radeon/rv6xx_dpm.c
1261
WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
sys/dev/drm/radeon/rv6xx_dpm.c
1268
WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
1270
WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
1381
WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
sys/dev/drm/radeon/rv6xx_dpm.c
1383
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/rv6xx_dpm.c
1385
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/rv6xx_dpm.c
1489
WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
sys/dev/drm/radeon/rv6xx_dpm.c
1491
WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
sys/dev/drm/radeon/rv6xx_dpm.c
318
WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
sys/dev/drm/radeon/rv6xx_dpm.c
325
WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
sys/dev/drm/radeon/rv6xx_dpm.c
333
WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
sys/dev/drm/radeon/rv6xx_dpm.c
336
WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
sys/dev/drm/radeon/rv6xx_dpm.c
343
WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
sys/dev/drm/radeon/rv6xx_dpm.c
349
WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
sys/dev/drm/radeon/rv6xx_dpm.c
356
WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);
sys/dev/drm/radeon/rv6xx_dpm.c
358
WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
sys/dev/drm/radeon/rv6xx_dpm.c
365
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/rv6xx_dpm.c
367
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/rv6xx_dpm.c
374
WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
sys/dev/drm/radeon/rv6xx_dpm.c
377
WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);
sys/dev/drm/radeon/rv6xx_dpm.c
383
WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
sys/dev/drm/radeon/rv6xx_dpm.c
390
WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
sys/dev/drm/radeon/rv6xx_dpm.c
397
WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
sys/dev/drm/radeon/rv6xx_dpm.c
403
WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);
sys/dev/drm/radeon/rv6xx_dpm.c
408
WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
sys/dev/drm/radeon/rv6xx_dpm.c
735
WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
737
WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
740
WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
742
WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
777
WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
779
WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);
sys/dev/drm/radeon/rv6xx_dpm.c
992
WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);
sys/dev/drm/radeon/rv6xx_dpm.c
994
WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);
sys/dev/drm/radeon/rv730_dpm.c
453
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/rv730_dpm.c
455
WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/rv730_dpm.c
457
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/rv730_dpm.c
469
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/rv730_dpm.c
471
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/rv730_dpm.c
473
WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/rv740_dpm.c
405
WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
sys/dev/drm/radeon/rv740_dpm.c
407
WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
sys/dev/drm/radeon/rv770.c
100
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
sys/dev/drm/radeon/rv770.c
107
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/rv770.c
112
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
sys/dev/drm/radeon/rv770.c
113
WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
sys/dev/drm/radeon/rv770.c
120
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/rv770.c
54
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/rv770.c
60
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
sys/dev/drm/radeon/rv770.c
75
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
sys/dev/drm/radeon/rv770.c
78
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
sys/dev/drm/radeon/rv770.c
81
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
sys/dev/drm/radeon/rv770.c
82
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
sys/dev/drm/radeon/rv770.c
89
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/rv770.c
92
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
sys/dev/drm/radeon/rv770.c
93
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/rv770_dpm.c
1341
WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
sys/dev/drm/radeon/rv770_dpm.c
1343
WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
sys/dev/drm/radeon/rv770_dpm.c
1370
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/rv770_dpm.c
1372
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
sys/dev/drm/radeon/rv770_dpm.c
138
WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/rv770_dpm.c
140
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/rv770_dpm.c
141
WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/rv770_dpm.c
142
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/rv770_dpm.c
1591
WREG32_P(GENERAL_PWRMGT, SW_SMIO_INDEX(0), ~SW_SMIO_INDEX_MASK);
sys/dev/drm/radeon/rv770_dpm.c
1637
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/rv770_dpm.c
1638
WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/rv770_dpm.c
1639
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/rv770_dpm.c
1643
WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
sys/dev/drm/radeon/rv770_dpm.c
1656
WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_ResumeFromMinimumPower),
sys/dev/drm/radeon/rv770_dpm.c
1668
WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/rv770_dpm.c
181
WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/rv770_dpm.c
1846
WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
sys/dev/drm/radeon/rv770_dpm.c
1848
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/rv770_dpm.c
1850
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/rv770_dpm.c
186
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/rv770_dpm.c
188
WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/rv770_dpm.c
1888
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
sys/dev/drm/radeon/rv770_dpm.c
1889
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
sys/dev/drm/radeon/rv770_dpm.c
1890
WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
sys/dev/drm/radeon/rv770_dpm.c
190
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/rv770_dpm.c
202
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/rv770_dpm.c
204
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/rv770_dpm.c
206
WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
sys/dev/drm/radeon/rv770_dpm.c
221
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/rv770_dpm.c
223
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/rv770_dpm.c
228
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
sys/dev/drm/radeon/rv770_dpm.c
779
WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN, ~BACKBIAS_PAD_EN);
sys/dev/drm/radeon/rv770_dpm.c
781
WREG32_P(GENERAL_PWRMGT, 0, ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN));
sys/dev/drm/radeon/rv770_dpm.c
791
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/rv770_dpm.c
798
WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
sys/dev/drm/radeon/rv770_dpm.c
800
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/rv770_dpm.c
802
WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
sys/dev/drm/radeon/rv770_dpm.c
846
WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
sys/dev/drm/radeon/rv770_dpm.c
858
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/rv770_dpm.c
860
WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/rv770_dpm.c
862
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
sys/dev/drm/radeon/rv770_dpm.c
864
WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
sys/dev/drm/radeon/rv770_dpm.c
879
WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
sys/dev/drm/radeon/rv770_smc.c
394
WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N);
sys/dev/drm/radeon/rv770_smc.c
399
WREG32_P(SMC_IO, 0, ~SMC_RST_N);
sys/dev/drm/radeon/rv770_smc.c
404
WREG32_P(SMC_IO, 0, ~SMC_CLK_EN);
sys/dev/drm/radeon/rv770_smc.c
409
WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN);
sys/dev/drm/radeon/rv770_smc.c
433
WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK);
sys/dev/drm/radeon/si.c
6361
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
sys/dev/drm/radeon/si.c
6998
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/si.c
7003
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
sys/dev/drm/radeon/si.c
7017
WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
sys/dev/drm/radeon/si.c
7020
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
sys/dev/drm/radeon/si.c
7023
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
sys/dev/drm/radeon/si.c
7026
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/si.c
7035
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/si.c
7038
WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
sys/dev/drm/radeon/si.c
7041
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
sys/dev/drm/radeon/si.c
7044
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
sys/dev/drm/radeon/si.c
7047
WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
sys/dev/drm/radeon/si.c
7049
WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
sys/dev/drm/radeon/si.c
7052
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/si.c
7060
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
sys/dev/drm/radeon/si.c
7065
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
sys/dev/drm/radeon/si.c
7072
WREG32_P(CG_UPLL_FUNC_CNTL_2,
sys/dev/drm/radeon/si_dpm.c
3308
WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
sys/dev/drm/radeon/si_dpm.c
3310
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/si_dpm.c
3312
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/si_dpm.c
3337
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/si_dpm.c
3342
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/si_dpm.c
3348
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/si_dpm.c
3350
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
sys/dev/drm/radeon/si_dpm.c
3595
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/si_dpm.c
3597
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
sys/dev/drm/radeon/si_dpm.c
3602
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
sys/dev/drm/radeon/si_dpm.c
3678
WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
sys/dev/drm/radeon/si_dpm.c
3679
WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
sys/dev/drm/radeon/si_dpm.c
3735
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/si_dpm.c
3737
WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
sys/dev/drm/radeon/si_dpm.c
3738
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
sys/dev/drm/radeon/si_dpm.c
3768
WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
sys/dev/drm/radeon/si_dpm.c
3780
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/si_dpm.c
3782
WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/si_dpm.c
3785
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
sys/dev/drm/radeon/si_dpm.c
3788
WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
sys/dev/drm/radeon/si_dpm.c
5716
WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
sys/dev/drm/radeon/si_dpm.c
5718
WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
sys/dev/drm/radeon/si_dpm.c
5998
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
sys/dev/drm/radeon/si_dpm.c
5999
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
sys/dev/drm/radeon/si_dpm.c
6000
WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
sys/dev/drm/radeon/si_smc.c
266
WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
sys/dev/drm/radeon/si_smc.c
276
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
sys/dev/drm/radeon/si_smc.c
42
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
sys/dev/drm/radeon/sumo_dpm.c
1174
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
sys/dev/drm/radeon/sumo_dpm.c
1175
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
sys/dev/drm/radeon/sumo_dpm.c
131
WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
sys/dev/drm/radeon/sumo_dpm.c
178
WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
sys/dev/drm/radeon/sumo_dpm.c
184
WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
sys/dev/drm/radeon/sumo_dpm.c
280
WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
sys/dev/drm/radeon/sumo_dpm.c
282
WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
sys/dev/drm/radeon/sumo_dpm.c
439
WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
sys/dev/drm/radeon/sumo_dpm.c
440
WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
sys/dev/drm/radeon/sumo_dpm.c
444
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/sumo_dpm.c
446
WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
sys/dev/drm/radeon/sumo_dpm.c
449
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
sys/dev/drm/radeon/sumo_dpm.c
452
WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
sys/dev/drm/radeon/sumo_dpm.c
483
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
486
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
489
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
492
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
568
WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
sys/dev/drm/radeon/sumo_dpm.c
574
WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
sys/dev/drm/radeon/sumo_dpm.c
589
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
592
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
595
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
598
WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
sys/dev/drm/radeon/sumo_dpm.c
612
WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
sys/dev/drm/radeon/sumo_dpm.c
617
WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
sys/dev/drm/radeon/sumo_dpm.c
623
WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
sys/dev/drm/radeon/sumo_dpm.c
625
WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
sys/dev/drm/radeon/sumo_dpm.c
731
WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
sys/dev/drm/radeon/sumo_dpm.c
778
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
sys/dev/drm/radeon/sumo_dpm.c
783
WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
sys/dev/drm/radeon/sumo_dpm.c
798
WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
sys/dev/drm/radeon/sumo_dpm.c
799
WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
sys/dev/drm/radeon/sumo_dpm.c
909
WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
sys/dev/drm/radeon/sumo_dpm.c
914
WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
sys/dev/drm/radeon/sumo_dpm.c
915
WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
sys/dev/drm/radeon/sumo_dpm.c
920
WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
sys/dev/drm/radeon/sumo_dpm.c
925
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
sys/dev/drm/radeon/sumo_dpm.c
94
WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/sumo_dpm.c
958
WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
sys/dev/drm/radeon/sumo_dpm.c
959
WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
sys/dev/drm/radeon/sumo_dpm.c
96
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/sumo_dpm.c
961
WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
sys/dev/drm/radeon/sumo_dpm.c
962
WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
sys/dev/drm/radeon/sumo_dpm.c
968
WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
sys/dev/drm/radeon/sumo_dpm.c
97
WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/sumo_dpm.c
98
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/sumo_dpm.c
995
WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
sys/dev/drm/radeon/sumo_dpm.c
997
WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
sys/dev/drm/radeon/trinity_dpm.c
1063
WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
sys/dev/drm/radeon/trinity_dpm.c
1064
WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
sys/dev/drm/radeon/trinity_dpm.c
394
WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK);
sys/dev/drm/radeon/trinity_dpm.c
451
WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/trinity_dpm.c
453
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
sys/dev/drm/radeon/trinity_dpm.c
454
WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/trinity_dpm.c
455
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
sys/dev/drm/radeon/trinity_dpm.c
466
WREG32_P(seq[i], seq[i+1], ~seq[i+2]);
sys/dev/drm/radeon/trinity_dpm.c
514
WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
sys/dev/drm/radeon/trinity_dpm.c
516
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN);
sys/dev/drm/radeon/trinity_dpm.c
767
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
sys/dev/drm/radeon/trinity_dpm.c
768
WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN);
sys/dev/drm/radeon/trinity_dpm.c
798
WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN);
sys/dev/drm/radeon/trinity_dpm.c
809
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
sys/dev/drm/radeon/trinity_dpm.c
814
WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,
sys/dev/drm/radeon/uvd_v1_0.c
227
WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
sys/dev/drm/radeon/uvd_v1_0.c
277
WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
sys/dev/drm/radeon/uvd_v1_0.c
280
WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
sys/dev/drm/radeon/uvd_v1_0.c
281
WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
sys/dev/drm/radeon/uvd_v1_0.c
291
WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
sys/dev/drm/radeon/uvd_v1_0.c
321
WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
sys/dev/drm/radeon/uvd_v1_0.c
323
WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
sys/dev/drm/radeon/uvd_v1_0.c
342
WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
sys/dev/drm/radeon/uvd_v1_0.c
344
WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
sys/dev/drm/radeon/uvd_v1_0.c
355
WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
sys/dev/drm/radeon/uvd_v1_0.c
379
WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
sys/dev/drm/radeon/uvd_v1_0.c
397
WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
sys/dev/drm/radeon/uvd_v1_0.c
398
WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
sys/dev/drm/radeon/uvd_v1_0.c
409
WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
sys/dev/drm/radeon/uvd_v1_0.c
410
WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
sys/dev/drm/radeon/vce_v1_0.c
223
WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
sys/dev/drm/radeon/vce_v1_0.c
224
WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
sys/dev/drm/radeon/vce_v1_0.c
225
WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
sys/dev/drm/radeon/vce_v1_0.c
228
WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);
sys/dev/drm/radeon/vce_v1_0.c
231
WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
sys/dev/drm/radeon/vce_v1_0.c
253
WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
sys/dev/drm/radeon/vce_v1_0.c
296
WREG32_P(VCE_STATUS, 1, ~1);
sys/dev/drm/radeon/vce_v1_0.c
312
WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);
sys/dev/drm/radeon/vce_v1_0.c
314
WREG32_P(VCE_SOFT_RESET,
sys/dev/drm/radeon/vce_v1_0.c
322
WREG32_P(VCE_SOFT_RESET, 0, ~(
sys/dev/drm/radeon/vce_v1_0.c
339
WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET);
sys/dev/drm/radeon/vce_v1_0.c
341
WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET);
sys/dev/drm/radeon/vce_v1_0.c
347
WREG32_P(VCE_STATUS, 0, ~1);
sys/dev/drm/radeon/vce_v2_0.c
162
WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
sys/dev/drm/radeon/vce_v2_0.c
163
WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
sys/dev/drm/radeon/vce_v2_0.c
164
WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
sys/dev/drm/radeon/vce_v2_0.c
168
WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
sys/dev/drm/radeon/vce_v2_0.c
190
WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
sys/dev/drm/radeon/vce_v2_0.c
192
WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,