sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1616

WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1617

WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1623

WREG32_NO_KIQ(mmMM_DATA, value);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2296

WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2297

WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2344

WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2345

WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2346

WREG32_NO_KIQ(mmMM_DATA, value);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

397

WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

141

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

143

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

145

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

147

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

230

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

282

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

326

WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

349

WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

360

WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

507

WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

537

WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/soc15_common.h

45

WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)

sys/dev/drm/amd/amdgpu/vega10_ih.c

217

WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);

sys/dev/drm/amd/amdgpu/vi.c

115

WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));