sys/dev/drm/amd/amdgpu/amdgpu_cgs.c

91

return WREG32_IDX(index, value);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2283

WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2300

WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2362

WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2379

WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2183

WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2198

WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_combios.c

3244

WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);

sys/dev/drm/radeon/radeon_cursor.c

66

WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

70

WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

84

WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);