sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

692

WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);

sys/dev/drm/amd/amdgpu/df_v1_7.c

108

WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1065

WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1966

WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2227

WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2424

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2431

WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2433

WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2443

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3025

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3118

WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3420

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4530

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4600

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4619

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

105

WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

304

WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1121

WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1155

WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1158

WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

94

WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

91

WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

89

WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);