WREG32_FIELD - DragonflyBSD

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

580

WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3835

WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4051

WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4090

WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4097

WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4105

WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4106

WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4113

WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4119

WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4124

WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4150

WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4158

WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4161

WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4167

WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4489

WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4660

WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4764

WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5393

WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5399

WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5405

WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5411

WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5417

WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5674

WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5677

WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6524

WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6584

WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6595

WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6660

WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6661

WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6662

WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6663

WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6664

WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6665

WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6667

WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6669

WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6671

WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6673

WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6675

WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6677

WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6679

WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6705

WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

616

WREG32_FIELD(UVD_CGC_GATE, REGS, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

725

WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

728

WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

744

WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

779

WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

799

WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

801

WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

846

WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

201

WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

257

WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

258

WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

260

WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

515

WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

166

WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

250

WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

252

WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

304

WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

309

WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

311

WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

317

WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

346

WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

349

WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

578

WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

727

WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

829

WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

714

WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

719

WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

724

WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

906

WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

925

WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);