sys/dev/drm/i915/intel_workarounds.c

129

WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);

sys/dev/drm/i915/intel_workarounds.c

132

WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);

sys/dev/drm/i915/intel_workarounds.c

135

WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

sys/dev/drm/i915/intel_workarounds.c

144

WA_SET_BIT_MASKED(HDC_CHICKEN0,

sys/dev/drm/i915/intel_workarounds.c

159

WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);

sys/dev/drm/i915/intel_workarounds.c

185

WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);

sys/dev/drm/i915/intel_workarounds.c

192

WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

195

WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,

sys/dev/drm/i915/intel_workarounds.c

198

WA_SET_BIT_MASKED(HDC_CHICKEN0,

sys/dev/drm/i915/intel_workarounds.c

216

WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);

sys/dev/drm/i915/intel_workarounds.c

219

WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);

sys/dev/drm/i915/intel_workarounds.c

232

WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

234

WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,

sys/dev/drm/i915/intel_workarounds.c

240

WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

sys/dev/drm/i915/intel_workarounds.c

246

WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,

sys/dev/drm/i915/intel_workarounds.c

251

WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,

sys/dev/drm/i915/intel_workarounds.c

257

WA_SET_BIT_MASKED(CACHE_MODE_1,

sys/dev/drm/i915/intel_workarounds.c

266

WA_SET_BIT_MASKED(HDC_CHICKEN0,

sys/dev/drm/i915/intel_workarounds.c

284

WA_SET_BIT_MASKED(HDC_CHICKEN0,

sys/dev/drm/i915/intel_workarounds.c

291

WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,

sys/dev/drm/i915/intel_workarounds.c

295

WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);

sys/dev/drm/i915/intel_workarounds.c

318

WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);

sys/dev/drm/i915/intel_workarounds.c

383

WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

sys/dev/drm/i915/intel_workarounds.c

387

WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

403

WA_SET_BIT_MASKED(HDC_CHICKEN0,

sys/dev/drm/i915/intel_workarounds.c

408

WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

412

WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,

sys/dev/drm/i915/intel_workarounds.c

427

WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

442

WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

446

WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,

sys/dev/drm/i915/intel_workarounds.c

455

WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,

sys/dev/drm/i915/intel_workarounds.c

460

WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);

sys/dev/drm/i915/intel_workarounds.c

463

WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

468

WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

472

WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);

sys/dev/drm/i915/intel_workarounds.c

475

WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);

sys/dev/drm/i915/intel_workarounds.c

486

WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);

sys/dev/drm/i915/intel_workarounds.c

497

WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

507

WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);

sys/dev/drm/i915/intel_workarounds.c

513

WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,

sys/dev/drm/i915/intel_workarounds.c

517

WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,

sys/dev/drm/i915/intel_workarounds.c

522

WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,