sys/dev/drm/amd/amdgpu/ci_dpm.c

3768

table->VceBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4275

pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4278

tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1561

offsetof(SMU7_Fusion_DpmTable, VceBootLevel),

sys/dev/drm/amd/powerplay/inc/smu72_discrete.h

280

uint8_t VceBootLevel;

sys/dev/drm/amd/powerplay/inc/smu73_discrete.h

264

uint8_t VceBootLevel;

sys/dev/drm/amd/powerplay/inc/smu74_discrete.h

298

uint8_t VceBootLevel;

sys/dev/drm/amd/powerplay/inc/smu75_discrete.h

304

uint8_t VceBootLevel;

sys/dev/drm/amd/powerplay/inc/smu7_discrete.h

338

uint8_t VceBootLevel;

sys/dev/drm/amd/powerplay/inc/smu7_fusion.h

241

uint8_t VceBootLevel;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1567

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2011

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2905

VceBootLevel, 0); /* temp hard code to level 0, vce can set min evclk*/

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1434

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2329

case VceBootLevel:

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2330

return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2407

smu_data->smc_state_table.VceBootLevel =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2410

smu_data->smc_state_table.VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2413

offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2419

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2426

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1299

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2160

smu_data->smc_state_table.VceBootLevel =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2163

smu_data->smc_state_table.VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2166

offsetof(SMU74_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2172

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2179

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2285

case VceBootLevel:

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2286

return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1381

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2637

case VceBootLevel:

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2638

return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2716

smu_data->smc_state_table.VceBootLevel =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2720

offsetof(SMU72_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2726

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2734

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1218

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2193

case VceBootLevel:

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2194

return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

373

smu_data->smc_state_table.VceBootLevel =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

376

smu_data->smc_state_table.VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

379

offsetof(SMU75_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

385

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

392

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);

sys/dev/drm/radeon/ci_dpm.c

3657

table->VceBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

4161

pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);

sys/dev/drm/radeon/ci_dpm.c

4164

tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);

sys/dev/drm/radeon/kv_dpm.c

1490

offsetof(SMU7_Fusion_DpmTable, VceBootLevel),

sys/dev/drm/radeon/smu7_discrete.h

337

uint8_t VceBootLevel;

sys/dev/drm/radeon/smu7_fusion.h

241

uint8_t VceBootLevel;