sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

147

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

148

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

637

tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

638

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

865

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

866

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

167

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

168

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/drm/radeon/cik.c

5471

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/drm/radeon/cik.c

5588

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/evergreen.c

2395

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/evergreen.c

2448

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/evergreen.c

2478

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/ni.c

1310

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/drm/radeon/ni.c

1389

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/r600.c

1136

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/r600.c

1228

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/rv770.c

906

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/rv770.c

952

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/rv770.c

983

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/si.c

4297

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/drm/radeon/si.c

4383

WREG32(VM_L2_CNTL2, 0);