Symbol: VM_L2_CNTL
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
136
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
137
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
139
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
141
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
142
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
143
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
304
WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
629
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
630
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
631
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
632
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
633
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
634
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
635
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
748
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
856
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
857
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
858
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
859
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
860
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
861
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
862
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
992
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
156
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
157
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
159
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
161
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
162
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
163
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
337
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/radeon/cik.c
5465
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
sys/dev/drm/radeon/cik.c
5582
WREG32(VM_L2_CNTL,
sys/dev/drm/radeon/evergreen.c
2392
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/evergreen.c
2446
WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/evergreen.c
2475
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/ni.c
1304
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
sys/dev/drm/radeon/ni.c
1385
WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
sys/dev/drm/radeon/r600.c
1133
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/r600.c
1187
WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/r600.c
1225
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/rv770.c
903
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/rv770.c
950
WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/rv770.c
980
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/si.c
4291
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
sys/dev/drm/radeon/si.c
4379
WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |