Symbol: VM_CONTEXT1_CNTL
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
211
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
212
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
214
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
216
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
219
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
221
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
223
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
225
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
227
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
229
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
233
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
520
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
522
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
524
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
526
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
528
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
530
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
685
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
686
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
687
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
745
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
747
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
749
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
751
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
753
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
755
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
757
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
928
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
929
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
930
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
931
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
932
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
933
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
934
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
935
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
936
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
937
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
230
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
231
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
233
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
235
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
238
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
240
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
242
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
244
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
246
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
248
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
252
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/radeon/cik.c
5506
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
sys/dev/drm/radeon/cik.c
5577
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/drm/radeon/evergreen.c
2427
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/drm/radeon/evergreen.c
2443
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/drm/radeon/evergreen.c
2493
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/drm/radeon/ni.c
1345
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
sys/dev/drm/radeon/ni.c
1379
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/drm/radeon/si.c
4336
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
sys/dev/drm/radeon/si.c
4374
WREG32(VM_CONTEXT1_CNTL, 0);