sys/dev/drm/i915/i915_pci.c

359

.display_mmio_offset = VLV_DISPLAY_BASE,

sys/dev/drm/i915/i915_pci.c

451

.display_mmio_offset = VLV_DISPLAY_BASE,

sys/dev/drm/i915/i915_reg.h

1000

#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)

sys/dev/drm/i915/i915_reg.h

10005

#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)

sys/dev/drm/i915/i915_reg.h

10006

#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)

sys/dev/drm/i915/i915_reg.h

1001

#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)

sys/dev/drm/i915/i915_reg.h

10012

#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)

sys/dev/drm/i915/i915_reg.h

1170

#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)

sys/dev/drm/i915/i915_reg.h

2510

#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)

sys/dev/drm/i915/i915_reg.h

2613

#define VLV_MIPI_BASE VLV_DISPLAY_BASE

sys/dev/drm/i915/i915_reg.h

2616

#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)

sys/dev/drm/i915/i915_reg.h

2617

#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)

sys/dev/drm/i915/i915_reg.h

2623

#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)

sys/dev/drm/i915/i915_reg.h

2626

#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)

sys/dev/drm/i915/i915_reg.h

2627

#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)

sys/dev/drm/i915/i915_reg.h

2628

#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)

sys/dev/drm/i915/i915_reg.h

2629

#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)

sys/dev/drm/i915/i915_reg.h

2630

#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)

sys/dev/drm/i915/i915_reg.h

2631

#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)

sys/dev/drm/i915/i915_reg.h

2632

#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)

sys/dev/drm/i915/i915_reg.h

2805

#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)

sys/dev/drm/i915/i915_reg.h

2943

#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)

sys/dev/drm/i915/i915_reg.h

2947

#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)

sys/dev/drm/i915/i915_reg.h

2950

#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)

sys/dev/drm/i915/i915_reg.h

2951

#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)

sys/dev/drm/i915/i915_reg.h

2952

#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)

sys/dev/drm/i915/i915_reg.h

3215

#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)

sys/dev/drm/i915/i915_reg.h

3217

#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)

sys/dev/drm/i915/i915_reg.h

3228

#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)

sys/dev/drm/i915/i915_reg.h

3313

#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)

sys/dev/drm/i915/i915_reg.h

3460

#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)

sys/dev/drm/i915/i915_reg.h

3463

#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)

sys/dev/drm/i915/i915_reg.h

3465

#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)

sys/dev/drm/i915/i915_reg.h

3470

#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)

sys/dev/drm/i915/i915_reg.h

3477

#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)

sys/dev/drm/i915/i915_reg.h

4090

#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)

sys/dev/drm/i915/i915_reg.h

4091

#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)

sys/dev/drm/i915/i915_reg.h

4105

#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)

sys/dev/drm/i915/i915_reg.h

4106

#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)

sys/dev/drm/i915/i915_reg.h

4112

#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)

sys/dev/drm/i915/i915_reg.h

4113

#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)

sys/dev/drm/i915/i915_reg.h

4253

#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)

sys/dev/drm/i915/i915_reg.h

4402

#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)

sys/dev/drm/i915/i915_reg.h

4403

#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)

sys/dev/drm/i915/i915_reg.h

4404

#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)

sys/dev/drm/i915/i915_reg.h

4610

#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)

sys/dev/drm/i915/i915_reg.h

5311

#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)

sys/dev/drm/i915/i915_reg.h

5312

#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)

sys/dev/drm/i915/i915_reg.h

5313

#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)

sys/dev/drm/i915/i915_reg.h

5668

#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)

sys/dev/drm/i915/i915_reg.h

5689

#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */

sys/dev/drm/i915/i915_reg.h

5734

#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */

sys/dev/drm/i915/i915_reg.h

5747

#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */

sys/dev/drm/i915/i915_reg.h

5792

#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)

sys/dev/drm/i915/i915_reg.h

5799

#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)

sys/dev/drm/i915/i915_reg.h

5808

#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)

sys/dev/drm/i915/i915_reg.h

5811

#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)

sys/dev/drm/i915/i915_reg.h

5812

#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */

sys/dev/drm/i915/i915_reg.h

5821

#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)

sys/dev/drm/i915/i915_reg.h

5830

#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */

sys/dev/drm/i915/i915_reg.h

5841

#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)

sys/dev/drm/i915/i915_reg.h

5862

#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)

sys/dev/drm/i915/i915_reg.h

5885

#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))

sys/dev/drm/i915/i915_reg.h

5893

#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)

sys/dev/drm/i915/i915_reg.h

5897

#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)

sys/dev/drm/i915/i915_reg.h

6378

#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)

sys/dev/drm/i915/i915_reg.h

6401

#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)

sys/dev/drm/i915/i915_reg.h

6402

#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)

sys/dev/drm/i915/i915_reg.h

6403

#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)

sys/dev/drm/i915/i915_reg.h

6404

#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)

sys/dev/drm/i915/i915_reg.h

6405

#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)

sys/dev/drm/i915/i915_reg.h

6406

#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)

sys/dev/drm/i915/i915_reg.h

6407

#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)

sys/dev/drm/i915/i915_reg.h

6408

#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)

sys/dev/drm/i915/i915_reg.h

6409

#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)

sys/dev/drm/i915/i915_reg.h

6410

#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)

sys/dev/drm/i915/i915_reg.h

6412

#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)

sys/dev/drm/i915/i915_reg.h

6415

#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)

sys/dev/drm/i915/i915_reg.h

6418

#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)

sys/dev/drm/i915/i915_reg.h

6420

#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)

sys/dev/drm/i915/i915_reg.h

6421

#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)

sys/dev/drm/i915/i915_reg.h

6422

#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)

sys/dev/drm/i915/i915_reg.h

6423

#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)

sys/dev/drm/i915/i915_reg.h

6424

#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)

sys/dev/drm/i915/i915_reg.h

6425

#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)

sys/dev/drm/i915/i915_reg.h

6426

#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)

sys/dev/drm/i915/i915_reg.h

6427

#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)

sys/dev/drm/i915/i915_reg.h

6428

#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)

sys/dev/drm/i915/i915_reg.h

6429

#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)

sys/dev/drm/i915/i915_reg.h

6430

#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)

sys/dev/drm/i915/i915_reg.h

6431

#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)

sys/dev/drm/i915/i915_reg.h

6432

#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)

sys/dev/drm/i915/i915_reg.h

6433

#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)

sys/dev/drm/i915/i915_reg.h

6461

_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))

sys/dev/drm/i915/i915_reg.h

6725

#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)

sys/dev/drm/i915/i915_reg.h

7893

#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)

sys/dev/drm/i915/i915_reg.h

7894

#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)

sys/dev/drm/i915/i915_reg.h

7895

#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)

sys/dev/drm/i915/i915_reg.h

7897

#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)

sys/dev/drm/i915/i915_reg.h

7898

#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)

sys/dev/drm/i915/i915_reg.h

7899

#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)

sys/dev/drm/i915/i915_reg.h

7901

#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)

sys/dev/drm/i915/i915_reg.h

7902

#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)

sys/dev/drm/i915/i915_reg.h

7903

#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)

sys/dev/drm/i915/i915_reg.h

8472

#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)

sys/dev/drm/i915/i915_reg.h

8730

#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)

sys/dev/drm/i915/i915_reg.h

8731

#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)

sys/dev/drm/i915/i915_reg.h

8733

#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)

sys/dev/drm/i915/i915_reg.h

8734

#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)

sys/dev/drm/i915/i915_reg.h

8736

#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)

sys/dev/drm/i915/i915_reg.h

8750

#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)

sys/dev/drm/i915/i915_reg.h

8751

#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)

sys/dev/drm/i915/i915_reg.h

9761

#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)

sys/dev/drm/i915/i915_reg.h

9762

#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)

sys/dev/drm/i915/i915_reg.h

9763

#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)

sys/dev/drm/i915/i915_reg.h

9764

#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)

sys/dev/drm/i915/i915_reg.h

9765

#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)

sys/dev/drm/i915/i915_reg.h

9766

#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)

sys/dev/drm/i915/i915_reg.h

9767

#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)

sys/dev/drm/i915/i915_reg.h

9768

#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)

sys/dev/drm/i915/i915_reg.h

9773

#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)

sys/dev/drm/i915/i915_reg.h

9774

#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)

sys/dev/drm/i915/i915_reg.h

9775

#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)

sys/dev/drm/i915/i915_reg.h

9776

#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)

sys/dev/drm/i915/i915_reg.h

9777

#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)

sys/dev/drm/i915/i915_reg.h

9778

#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)

sys/dev/drm/i915/i915_reg.h

9779

#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)

sys/dev/drm/i915/i915_reg.h

978

#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)

sys/dev/drm/i915/i915_reg.h

9780

#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)

sys/dev/drm/i915/i915_reg.h

9942

#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)

sys/dev/drm/i915/i915_reg.h

9943

#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)

sys/dev/drm/i915/intel_i2c.c

824

dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;