sys/dev/drm/amd/amdgpu/ci_dpm.c

3767

table->UvdBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4231

pi->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4233

pi->smc_state_table.UvdBootLevel =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4238

tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1516

offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),

sys/dev/drm/amd/powerplay/inc/smu72_discrete.h

279

uint8_t UvdBootLevel;

sys/dev/drm/amd/powerplay/inc/smu73_discrete.h

263

uint8_t UvdBootLevel;

sys/dev/drm/amd/powerplay/inc/smu74_discrete.h

297

uint8_t UvdBootLevel;

sys/dev/drm/amd/powerplay/inc/smu75_discrete.h

303

uint8_t UvdBootLevel;

sys/dev/drm/amd/powerplay/inc/smu7_discrete.h

337

uint8_t UvdBootLevel;

sys/dev/drm/amd/powerplay/inc/smu7_fusion.h

240

uint8_t UvdBootLevel;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2010

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2869

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2871

smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2874

UvdBootLevel, smu_data->smc_state_table.UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1570

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2327

case UvdBootLevel:

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2328

return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2373

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2375

smu_data->smc_state_table.UvdBootLevel =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2378

UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2384

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2394

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1405

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2126

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2128

smu_data->smc_state_table.UvdBootLevel =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2131

UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2137

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2147

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2283

case UvdBootLevel:

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2284

return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1321

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2635

case UvdBootLevel:

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2636

return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2681

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2683

smu_data->smc_state_table.UvdBootLevel =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2686

offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2692

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2703

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1331

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2191

case UvdBootLevel:

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2192

return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

339

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

341

smu_data->smc_state_table.UvdBootLevel =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

344

UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

350

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

360

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));

sys/dev/drm/radeon/ci_dpm.c

3656

table->UvdBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

4119

pi->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

4121

pi->smc_state_table.UvdBootLevel =

sys/dev/drm/radeon/ci_dpm.c

4126

tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);

sys/dev/drm/radeon/kv_dpm.c

1442

offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),

sys/dev/drm/radeon/smu7_discrete.h

336

uint8_t UvdBootLevel;

sys/dev/drm/radeon/smu7_fusion.h

240

uint8_t UvdBootLevel;