Symbol: UVD_RBC_RB_CNTL
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
396
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
397
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
398
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
399
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
400
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
401
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
820
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
821
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
822
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
823
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
824
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
825
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
846
WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1067
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1068
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1069
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1070
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1071
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1072
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
900
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
901
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1066
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1067
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1068
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1069
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1070
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
893
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
894
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
895
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
896
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
897
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/radeon/uvd_v1_0.c
358
WREG32(UVD_RBC_RB_CNTL, 0x11010101);
sys/dev/drm/radeon/uvd_v1_0.c
379
WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
sys/dev/drm/radeon/uvd_v1_0.c
394
WREG32(UVD_RBC_RB_CNTL, 0x11010101);