BASE
#define ROLL(BASE,INTERVAL) floor((BASE) + (INTERVAL) * drandom())
if (Sect[i][j] == BASE) {
Sect[rx][ry] = BASE;
case BASE:
case BASE:
case BASE:
#define _REL(BASE) ((int)item-BASE)
base = itobn(BASE);
r = seed[i] % BASE;
adler -= BASE;
sum1 += (adler2 & 0xffff) + BASE - 1;
sum2 += ((adler1 >> 16) & 0xffff) + ((adler2 >> 16) & 0xffff) + BASE - rem;
if (sum1 >= BASE) sum1 -= BASE;
if (sum1 >= BASE) sum1 -= BASE;
if (sum2 >= (BASE << 1)) sum2 -= (BASE << 1);
if (sum2 >= BASE) sum2 -= BASE;
if (a >= BASE) a -= BASE; \
if (a >= BASE) a -= BASE; \
# define MOD(a) a %= BASE
# define MOD28(a) a %= BASE
# define MOD63(a) a %= BASE
if (adler >= BASE)
adler -= BASE;
if (sum2 >= BASE)
sum2 -= BASE;
if (adler >= BASE)
data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
insw(BASE + DATA_REG_W, data, packet_length >> 1);
*data = inb(BASE + DATA_REG_B);
while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
outw(BASE + MMU_CMD_REG_W, MMUCR_RELEASE);
packet_number = inw(BASE + FIFO_PORTS_REG_W);
outb(BASE + INTR_MASK_REG_B, 0x00);
outw(BASE + RECV_CONTROL_REG_W, 0x0000);
outw(BASE + TXMIT_CONTROL_REG_W, 0x0000);
outw(BASE + MULTICAST1_REG_W,
outw(BASE + MULTICAST2_REG_W,
outw(BASE + MULTICAST3_REG_W,
outw(BASE + MULTICAST4_REG_W,
outw(BASE + RECV_CONTROL_REG_W, flags);
rev = inw(BASE + REVISION_REG_W);
i = inw(BASE + CONFIG_REG_W);
outw(BASE + IAR_ADDR0_REG_W + j * 2, w);
address = inw(BASE + IAR_ADDR0_REG_W + i);
outw(BASE + RECV_CONTROL_REG_W, RCR_SOFTRESET);
outw(BASE + RECV_CONTROL_REG_W, 0x0000);
outw(BASE + TXMIT_CONTROL_REG_W, 0x0000);
outw(BASE + CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
flags = inw(BASE + CONFIG_REG_W);
outw(BASE + CONFIG_REG_W, flags);
outw(BASE + MMU_CMD_REG_W, MMUCR_RESET);
while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
outb(BASE + INTR_MASK_REG_B, 0x00);
outw(BASE + TXMIT_CONTROL_REG_W, flags);
outb(BASE + INTR_MASK_REG_B, mask);
outw(BASE + MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
if (inb(BASE + INTR_STAT_REG_B) & IM_ALLOC_INT)
mask = inb(BASE + INTR_MASK_REG_B) | IM_ALLOC_INT;
outb(BASE + INTR_MASK_REG_B, mask);
packet_no = inb(BASE + ALLOC_RESULT_REG_B);
outb(BASE + PACKET_NUM_REG_B, packet_no);
outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
outw(BASE + DATA_REG_W, 0);
outb(BASE + DATA_REG_B, (length + 6) & 0xFF);
outb(BASE + DATA_REG_B, (length + 6) >> 8);
outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2);
outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1));
outw(BASE + DATA_REG_W, 0);
outb(BASE + DATA_REG_B, 0);
outw(BASE + DATA_REG_W, 0);
mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
outb(BASE + INTR_MASK_REG_B, mask);
outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
if (inw(BASE + FIFO_PORTS_REG_W) & FIFO_REMPTY)
packet_no = inb(BASE + ALLOC_RESULT_REG_B);
outb(BASE + PACKET_NUM_REG_B, packet_no);
while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
outw(BASE + DATA_REG_W, 0);
outb(BASE + DATA_REG_B, (length + 6) & 0xFF);
outb(BASE + DATA_REG_B, (length + 6) >> 8);
outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2);
outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1));
outw(BASE + DATA_REG_W, 0);
outb(BASE + DATA_REG_B, 0);
outw(BASE + DATA_REG_W, 0);
mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
outb(BASE + INTR_MASK_REG_B, mask);
outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
mask = inb(BASE + INTR_MASK_REG_B);
outb(BASE + INTR_MASK_REG_B, 0x00);
interrupts = inb(BASE + INTR_STAT_REG_B);
outb(BASE + INTR_ACK_REG_B, IM_RX_OVRN_INT);
packet_number = inw(BASE + FIFO_PORTS_REG_W);
outb(BASE + INTR_ACK_REG_B, IM_TX_INT);
packet_no = inw(BASE + FIFO_PORTS_REG_W);
outb(BASE + PACKET_NUM_REG_B, packet_no);
outw(BASE + POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
tx_status = inw(BASE + DATA_REG_W);
outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE);
outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
outb(BASE + INTR_ACK_REG_B, IM_TX_EMPTY_INT);
card_stats = inw(BASE + COUNTER_REG_W);
mask |= inb(BASE + INTR_MASK_REG_B);
outb(BASE + INTR_MASK_REG_B, mask);
packet_number = inw(BASE + FIFO_PORTS_REG_W);
outw(BASE + POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
status = inw(BASE + DATA_REG_W);
packet_length = inw(BASE + DATA_REG_W) & RLEN_MASK;
#define SMC_SELECT_BANK(x) { outw( BASE + BANK_SELECT_REG_W, (x) ); }
#define SMC_DELAY() { inw( BASE + RECV_CONTROL_REG_W );\
inw( BASE + RECV_CONTROL_REG_W );\
inw( BASE + RECV_CONTROL_REG_W ); }
s1 %= BASE;
s2 %= BASE;
adler -= BASE;
sum1 += (adler2 & 0xffff) + BASE - 1;
sum2 += ((adler1 >> 16) & 0xffff) + ((adler2 >> 16) & 0xffff) + BASE - rem;
if (sum1 >= BASE) sum1 -= BASE;
if (sum1 >= BASE) sum1 -= BASE;
if (sum2 >= (BASE << 1)) sum2 -= (BASE << 1);
if (sum2 >= BASE) sum2 -= BASE;
if (a >= BASE) a -= BASE; \
if (a >= BASE) a -= BASE; \
# define MOD(a) a %= BASE
# define MOD28(a) a %= BASE
# define MOD63(a) a %= BASE
if (adler >= BASE)
adler -= BASE;
if (sum2 >= BASE)
sum2 -= BASE;
if (adler >= BASE)
base = itobn(BASE);
r = seed[i] % BASE;
adler -= BASE;
sum1 += (adler2 & 0xffff) + BASE - 1;
sum2 += ((adler1 >> 16) & 0xffff) + ((adler2 >> 16) & 0xffff) + BASE - rem;
if (sum1 >= BASE) sum1 -= BASE;
if (sum1 >= BASE) sum1 -= BASE;
if (sum2 >= (BASE << 1)) sum2 -= (BASE << 1);
if (sum2 >= BASE) sum2 -= BASE;
if (a >= BASE) a -= BASE; \
if (a >= BASE) a -= BASE; \
# define MOD(a) a %= BASE
# define MOD28(a) a %= BASE
# define MOD63(a) a %= BASE
if (adler >= BASE)
adler -= BASE;
if (sum2 >= BASE)
sum2 -= BASE;
if (adler >= BASE)