sys/dev/crypto/tpm/tpm.c

393

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);

sys/dev/crypto/tpm/tpm.c

454

burst = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS + 1);

sys/dev/crypto/tpm/tpm.c

455

burst |= bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS + 2)

sys/dev/crypto/tpm/tpm.c

477

status = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS) &

sys/dev/crypto/tpm/tpm.c

710

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,

sys/dev/crypto/tpm/tpm.c

750

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);

sys/dev/crypto/tpm/tpm.c

887

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,

sys/dev/crypto/tpm/tpm.c

904

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,

sys/dev/crypto/tpm/tpm_tis.c

285

burst_count = (RD4(sc, TPM_STS) & TPM_STS_BURST_MASK) >>

sys/dev/crypto/tpm/tpm_tis.c

390

WR4(sc, TPM_STS, TPM_STS_CMD_RDY);

sys/dev/crypto/tpm/tpm_tis.c

391

bus_barrier(sc->mem_res, TPM_STS, 4, BUS_SPACE_BARRIER_WRITE);

sys/dev/crypto/tpm/tpm_tis.c

392

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_B))

sys/dev/crypto/tpm/tpm_tis.c

425

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C)) {

sys/dev/crypto/tpm/tpm_tis.c

430

if (RD4(sc, TPM_STS) & TPM_STS_DATA_EXPECTED) {

sys/dev/crypto/tpm/tpm_tis.c

444

WR4(sc, TPM_STS, TPM_STS_CMD_START);

sys/dev/crypto/tpm/tpm_tis.c

445

bus_barrier(sc->mem_res, TPM_STS, 4, BUS_SPACE_BARRIER_WRITE);

sys/dev/crypto/tpm/tpm_tis.c

449

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, timeout)) {

sys/dev/crypto/tpm/tpm_tis.c

464

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C))