Symbol: TF_SF
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
182
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
183
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
184
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
185
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
186
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
187
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
188
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
189
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
190
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
191
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
192
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
193
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
194
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
195
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
196
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
197
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
198
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
199
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
200
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
201
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
202
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
203
TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
205
TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
206
TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
207
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
208
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
209
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
210
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
211
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
212
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
213
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
214
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
215
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
216
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
217
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
218
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
219
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
220
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
221
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
222
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
223
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
224
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
225
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
226
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
227
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
228
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
229
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
230
TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
231
TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
232
TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
233
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
234
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
235
TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
236
TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
237
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
238
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
239
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
240
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
241
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
242
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
243
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
244
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
245
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
246
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
247
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
248
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
249
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
250
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
251
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
252
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
253
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
254
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
255
TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
256
TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
257
TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
258
TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
259
TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
260
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
261
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
262
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
263
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
264
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
265
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
266
TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
267
TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
268
TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
269
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
270
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
271
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
272
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
273
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
274
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
275
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
276
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
277
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
278
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
279
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
280
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
281
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
282
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
283
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
284
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
285
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
286
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
287
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
288
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
289
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
290
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
291
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
292
TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
293
TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
294
TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
295
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
296
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
297
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
298
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
299
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
300
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
301
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
302
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
303
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
304
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
305
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
306
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
307
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
308
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
309
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
310
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
311
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
312
TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
313
TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
314
TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
315
TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
316
TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
317
TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
318
TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
319
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
321
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
322
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
323
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
324
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
325
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
326
TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
327
TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
328
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
329
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
330
TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
331
TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
335
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
336
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
337
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
338
TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
339
TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
340
TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
341
TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
342
TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
343
TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
344
TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
345
TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
346
TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
347
TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
348
TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
349
TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
350
TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
351
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
352
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
353
TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
354
TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
355
TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
356
TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
357
TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
358
TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
359
TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
360
TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
361
TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
362
TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
363
TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
364
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
365
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
366
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
367
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
368
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
369
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
370
TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
371
TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
372
TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
373
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
374
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
375
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
376
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
377
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
378
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
379
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
380
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
381
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
382
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
383
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
384
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
385
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
386
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
387
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
388
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
389
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
390
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
391
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
392
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
393
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
394
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
395
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
396
TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
397
TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
398
TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
399
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
400
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
401
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
402
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
403
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
404
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
405
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
406
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
407
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
408
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
409
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
410
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
411
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
412
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
413
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
414
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
415
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
416
TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
417
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
418
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
419
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
420
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
421
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
422
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
423
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
424
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
425
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
426
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
427
TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
428
TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
429
TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
430
TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
431
TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
432
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
433
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
434
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
435
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
436
TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)