sys/dev/drm/amd/amdgpu/kv_dpm.c

145

for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

165

for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2760

if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2810

for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)

sys/dev/drm/amd/amdgpu/kv_dpm.h

108

struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/amd/amdgpu/kv_dpm.h

133

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/amd/amdgpu/kv_dpm.h

55

struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/kv_dpm.c

2685

if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)

sys/dev/drm/radeon/kv_dpm.c

2735

for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)

sys/dev/drm/radeon/kv_dpm.h

107

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/kv_dpm.h

82

struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/sumo_dpm.c

1510

if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)

sys/dev/drm/radeon/sumo_dpm.c

1602

for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {

sys/dev/drm/radeon/sumo_dpm.c

1622

for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {

sys/dev/drm/radeon/sumo_dpm.c

396

u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/sumo_dpm.c

397

u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/sumo_dpm.h

45

struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/sumo_dpm.h

77

struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/trinity_dpm.c

1791

if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)

sys/dev/drm/radeon/trinity_dpm.c

1961

for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)

sys/dev/drm/radeon/trinity_dpm.c

724

if (index >= SUMO_MAX_HARDWARE_POWERLEVELS)

sys/dev/drm/radeon/trinity_dpm.h

49

struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/trinity_dpm.h

95

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];