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mmWD_CNTL_SB_BUF_BASE_HI
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
4895
#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
5180
#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
5136
#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255
