sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

5077

#define mmSPI_CONFIG_CNTL 0x2440

sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

5362

#define mmSPI_CONFIG_CNTL 0x2440

sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

5320

#define mmSPI_CONFIG_CNTL 0x2440

sys/dev/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

1194

#define mmSPI_CONFIG_CNTL 0x2440

sys/dev/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

1452

#define mmSPI_CONFIG_CNTL 0x2440

sys/dev/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

1473

#define mmSPI_CONFIG_CNTL 0x2440

sys/dev/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

1663

#define mmSPI_CONFIG_CNTL 0x2440

sys/dev/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

1631

#define mmSPI_CONFIG_CNTL 0x2440