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mmRMI_UTCL1_CNTL2
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
1080
#define mmRMI_UTCL1_CNTL2 0x078c
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
1098
#define mmRMI_UTCL1_CNTL2 0x078c
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
1064
#define mmRMI_UTCL1_CNTL2 0x078c
