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mmRLC_SPM_UTCL1_CNTL
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
6165
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
6442
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
6418
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
