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mmRLC_GPM_UTCL1_CNTL_2
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
6163
#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
6440
#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
6416
#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4
