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mmGC_DIDT_CTRL0
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
2899
#define mmGC_DIDT_CTRL0 0x128e
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
3186
#define mmGC_DIDT_CTRL0 0x128e
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
3142
#define mmGC_DIDT_CTRL0 0x128e
