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mmCP_RB0_WPTR_HI
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
2382
#define mmCP_RB0_WPTR_HI 0x1055
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
2696
#define mmCP_RB0_WPTR_HI 0x1055
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
2634
#define mmCP_RB0_WPTR_HI 0x1055
