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mmCP_HQD_PQ_WPTR_HI
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
2873
#define mmCP_HQD_PQ_WPTR_HI 0x127c
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
3156
#define mmCP_HQD_PQ_WPTR_HI 0x127c
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
3112
#define mmCP_HQD_PQ_WPTR_HI 0x127c
