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mmCPG_UTCL1_CNTL
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
2312
#define mmCPG_UTCL1_CNTL 0x103c
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
2626
#define mmCPG_UTCL1_CNTL 0x103c
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
2564
#define mmCPG_UTCL1_CNTL 0x103c
